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  august 2010 doc id 13829 rev 1 1/243 1 st72321xx-auto 8-bit mcu for automotive with 32/60 kbyte flash/rom, adc, 5 timers, spi, sci, i2c interface features memories 32 to 60 kbyte dual voltage high density flash (hdflash) or rom rom with readout protection capability. in-application programming and in-cir cuit programming for hdflash devices 1 to 2 kbyte ram hdflash endurance: 10 0 cycles, data retention 20 years clock, reset and supply management enhanced low voltage supervisor (lvd) for main supply and auxiliary voltage detector (avd) with interr upt capability clock sources: crysta l/ceramic resonator oscillators, internal rc oscillator and bypass for external clock pll for 2x frequency multiplication 4 power saving modes: halt, active halt, wait and slow interrupt management nested interr upt controller 14 interrupt vectors plus trap and reset top level interrupt (tli) pin on 64-pin devices 15 external interrupt lines (on 4 vectors) 1 analog peripheral 10-bit adc with up to 16 input ports up to 48 i/o ports 48//32 multifunctional bidirectional i/o lines 34//22 alternate function lines 16//12 high sink outputs 5 timers main clock controller with real-time base, beep and clock-out capabilities configurable watchdog timer two 16-bit timers with 2 input captures, 2 output compares, external clock input on 1 timer, pwm and pulse generator modes 8-bit pwm auto-reload timer with 2 input captures, 4 pwm outputs, output compare and time base interrupt, external clock with event detector 3 communications interfaces spi synchronous serial interface sci asynchronous serial interface i 2 c multimaster interface instruction set 8-bit data manipulation 63 basic instructions 17 main addressing modes 8x8 unsigned multiply instruction development tools full hardware/software development package, ict capability table 1. device summary reference part number st72321xx-auto st72321ar6-auto, st72321r6-auto, st72321ar7-auto, st72321j7-auto, st72321r7-auto ST72321AR9-AUTO, st72321j9-auto, st72321r9-auto lqfp64 10 x 10 lqfp64 14 x 14 lqfp44 10 x 10 www.st.com
contents st72321xx-auto 2/243 doc id 13829 rev 1 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2 package pinout and pin descripti on . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.1 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3 register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4 flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.3 structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.3.1 readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.4 icc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.5 icp (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.6 iap (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.7 related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.8 flash control/status register (fcsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5 central processing unit (cpu ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3.1 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3.2 index registers (x and y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3.3 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3.4 condition code (cc) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3.5 stack pointer (sp) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6 supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.3 phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
st72321xx-auto contents doc id 13829 rev 1 3/243 6.4 multi-oscillator (mo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.5 reset sequence manager (rsm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.5.2 asynchronous external reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.5.3 external power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.5.4 internal low voltage detector (lvd) reset . . . . . . . . . . . . . . . . . . . . . . 41 6.5.5 internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.6 system integrity management (si) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.6.1 low voltage detector (lvd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.6.2 auxiliary voltage detector (avd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.6.3 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.6.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.6.5 system integrity (si) control/status register (sicsr) . . . . . . . . . . . . . . 47 7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.2 masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.3 interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.4 concurrent and nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.5 interrupt register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.5.1 cpu cc register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.5.2 interrupt software priority registers (isprx) . . . . . . . . . . . . . . . . . . . . . . 54 7.6 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7.6.1 i/o port interrupt sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7.6.2 external interrupt control register (eicr) . . . . . . . . . . . . . . . . . . . . . . . . 59 8 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 8.2 slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 8.3 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 8.4 active halt and halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 8.4.1 active halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 8.4.2 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 9 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
contents st72321xx-auto 4/243 doc id 13829 rev 1 9.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 9.2.1 input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 9.2.2 output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 9.2.3 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 9.3 i/o port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 9.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 9.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 10 watchdog timer (wdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 10.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 10.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 10.4 how to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 10.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 10.6 hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 10.7 using halt mode with the wdg (wdghalt option) . . . . . . . . . . . . . . . . 80 10.8 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 10.9 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 10.9.1 control register (wdgcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 11 main clock controller with real-time clock and beeper (mcc/rtc) . . 82 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 11.2 programmable cpu clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 11.3 clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 11.4 real-time clock timer (rtc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 11.5 beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 11.6 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 11.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 11.8 main clock controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 11.8.1 mcc control/status register (mccsr) . . . . . . . . . . . . . . . . . . . . . . . . . . 84 11.8.2 mcc beep control register (mccbcr) . . . . . . . . . . . . . . . . . . . . . . . . . 85 12 pwm auto-reload timer (art) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 12.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 12.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
st72321xx-auto contents doc id 13829 rev 1 5/243 12.2.1 counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 12.2.2 counter clock and prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 12.2.3 counter and prescaler initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 12.2.4 output compare control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 12.2.5 independent pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 12.2.6 output compare and time base interrupt . . . . . . . . . . . . . . . . . . . . . . . . 90 12.2.7 external clock and event detector mode . . . . . . . . . . . . . . . . . . . . . . . . 90 12.2.8 input capture function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 12.2.9 external interrupt capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 12.3 art registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 12.3.1 control/status register (artcsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 12.3.2 counter access register (artcar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 12.3.3 auto-reload register (artarr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 12.3.4 pwm control register (pwmcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 12.3.5 duty cycle registers (pwmdcrx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 12.3.6 input capture control / status register (articcsr) . . . . . . . . . . . . . . . . 96 12.3.7 input capture registers (articrx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 13 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 13.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 13.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 13.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 13.3.1 counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 13.3.2 external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 13.3.3 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 13.3.4 output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 13.3.5 forced compare outp ut capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 13.3.6 one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 13.3.7 pulse width modulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 13.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 13.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 13.6 summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 13.7 16-bit timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 13.7.1 control register 1 (cr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 13.7.2 control register 2 (cr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 13.7.3 control/status register (csr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
contents st72321xx-auto 6/243 doc id 13829 rev 1 13.7.4 input capture 1 high register (ic1hr) . . . . . . . . . . . . . . . . . . . . . . . . . 116 13.7.5 input capture 1 low register (ic1lr) . . . . . . . . . . . . . . . . . . . . . . . . . . 117 13.7.6 output compare 1 high register (oc1hr) . . . . . . . . . . . . . . . . . . . . . . 117 13.7.7 output compare 1 low register (oc1lr) . . . . . . . . . . . . . . . . . . . . . . . 117 13.7.8 output compare 2 high register (oc2hr) . . . . . . . . . . . . . . . . . . . . . . 117 13.7.9 output compare 2 low register (oc2lr) . . . . . . . . . . . . . . . . . . . . . . . 118 13.7.10 counter high register (chr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 13.7.11 counter low register (clr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 13.7.12 alternate counter high register (achr) . . . . . . . . . . . . . . . . . . . . . . . . 118 13.7.13 alternate counter low register (aclr) . . . . . . . . . . . . . . . . . . . . . . . . . 119 13.7.14 input capture 2 high register (ic2hr) . . . . . . . . . . . . . . . . . . . . . . . . . 119 13.7.15 input capture 2 low register (ic2lr) . . . . . . . . . . . . . . . . . . . . . . . . . . 119 14 serial peripheral interface (spi ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 14.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 14.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 14.3.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 14.3.2 slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 14.3.3 master mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 14.3.4 master mode transmit sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 14.3.5 slave mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 14.3.6 slave mode transmit sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 14.4 clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 14.5 error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 14.5.1 master mode fault (modf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 14.5.2 overrun condition (ovr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 14.5.3 write collision error (wcol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 14.5.4 single master systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 14.6 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 14.6.1 using the spi to wake up the mcu from halt mode . . . . . . . . . . . . . . 130 14.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 14.8 spi registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 14.8.1 control register (spicr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 14.8.2 control/status register (spicsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 14.8.3 data i/o register (spidr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
st72321xx-auto contents doc id 13829 rev 1 7/243 15 serial communications interface (sci) . . . . . . . . . . . . . . . . . . . . . . . . 135 15.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 15.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 15.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 15.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 15.4.1 serial data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 15.4.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 15.4.3 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 15.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 15.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 15.7 sci registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 15.7.1 status register (scisr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 15.7.2 control register 1 (scicr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 15.7.3 control register 2 (scicr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 15.7.4 data register (scidr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 15.7.5 baud rate register (scibrr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 15.7.6 extended receive prescaler division register (scierpr) . . . . . . . . . . 152 15.7.7 extended transmit prescaler division register (scietpr) . . . . . . . . . . 153 16 i2c bus interface (i2c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 16.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 16.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 16.2.1 i2c master features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 16.2.2 i2c slave features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 16.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 16.3.1 mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 16.3.2 communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 16.3.3 sda/scl line control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 16.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 16.4.1 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 16.4.2 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 16.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 16.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 16.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 16.7.1 i2c control register (cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
contents st72321xx-auto 8/243 doc id 13829 rev 1 16.7.2 i2c status register 1 (sr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 16.7.3 i2c status register 2 (sr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 16.7.4 i2c clock control register (ccr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 16.7.5 i2c data register (dr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 16.7.6 i2c own address register (oar1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 16.7.7 i2c own address register (oar2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 17 10-bit a/d converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 17.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 17.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 17.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 17.3.1 a/d converter configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 17.3.2 starting the conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 17.3.3 changing the conversion channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 17.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 17.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 17.6 adc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 17.6.1 control/status register (adccsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 17.6.2 data register (adcdrh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 17.6.3 data register (adcdrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 17.6.4 adc register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 18 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 18.1 cpu addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 18.1.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 18.1.2 immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 18.1.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 18.1.4 indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 18.1.5 indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 18.1.6 indirect indexed (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 18.1.7 relative (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 18.2 instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 18.2.1 using a prebyte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 19 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 19.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
st72321xx-auto contents doc id 13829 rev 1 9/243 19.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 19.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 19.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 19.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 19.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 19.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 19.2.1 voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 19.2.2 current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 19.2.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 19.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 19.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 19.3.2 operating conditions with low voltage detector (lvd) . . . . . . . . . . . . . 189 19.3.3 auxiliary voltage detector (avd) thresholds . . . . . . . . . . . . . . . . . . . . . 189 19.3.4 external voltage detector (evd) thresholds . . . . . . . . . . . . . . . . . . . . . 190 19.4 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 19.4.1 current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 19.4.2 supply and clock managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 19.4.3 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 19.5 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 19.5.1 general timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 19.5.2 external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 19.5.3 crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 196 19.5.4 rc oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 19.5.5 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 19.6 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 19.6.1 ram and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 19.6.2 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 19.7 emc (electromagnetic compatibility) charac teristics . . . . . . . . . . . . . . . 200 19.7.1 functional ems (ele ctromagnetic susc eptibility) . . . . . . . . . . . . . . . . . 200 19.7.2 emi (electromagnetic interference) . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 19.7.3 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 202 19.8 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 19.8.1 general characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 19.8.2 output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 19.9 control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 19.9.1 asynchronous reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
contents st72321xx-auto 10/243 doc id 13829 rev 1 19.9.2 iccsel/v pp pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 19.10 timer peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 19.11 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 211 19.11.1 spi (serial peripheral interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 19.11.2 i 2 c - inter ic control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 19.12 10-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 19.12.1 analog power supply and reference pins . . . . . . . . . . . . . . . . . . . . . . . 217 19.12.2 general pcb design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 19.12.3 adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 20 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 20.1 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 20.2 ecopack information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 20.3 packaging for automatic handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 21 device configuration and ordering informati on . . . . . . . . . . . . . . . . . 223 21.1 flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 21.1.1 flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 21.1.2 flash ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 21.2 rom device ordering information and transfer of customer code . . . . . 227 21.3 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 21.3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 21.3.2 evaluation tools and starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 21.3.3 development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 21.3.4 programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 21.3.5 socket and emulator adapter information . . . . . . . . . . . . . . . . . . . . . . 232 21.4 st7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 22 known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 22.1 all flash and rom devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 22.1.1 external rc option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 22.1.2 safe connection of osc1/osc2 pins . . . . . . . . . . . . . . . . . . . . . . . . . 234 22.1.3 reset pin protection with lvd enabled . . . . . . . . . . . . . . . . . . . . . . . . 234 22.1.4 unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 22.1.5 external interrupt missed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 22.1.6 clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . 238
st72321xx-auto contents doc id 13829 rev 1 11/243 22.1.7 sci wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 22.1.8 16-bit timer pwm mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 22.1.9 timd set simultaneously with oc interrupt . . . . . . . . . . . . . . . . . . . . . 240 22.1.10 i 2 c multimaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 22.1.11 readout protection with lvd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 22.2 all flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 22.2.1 internal rc oscillator with lvd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 22.3 limitations specific to rom devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 22.3.1 lvd operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 22.3.2 lvd startup behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 22.3.3 avd not supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 22.3.4 internal rc oscillator operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 22.3.5 external clock source with pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 22.3.6 pull-up not present on pe2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 22.3.7 readout protection with lvd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 23 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
list of tables st72321xx-auto 12/243 doc id 13829 rev 1 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 3. device pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 4. hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 5. sectors available in flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 6. flash control/status register address and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 7. arithmetic management bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 8. interrupt management bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 9. interrupt software priority selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 10. st7 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 11. effect of low power modes on si . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 12. avd interrupt control/ wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 table 13. sicsr description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 14. reset source flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 15. interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 16. cpu cc register interrupt bits description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 table 17. interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 18. interrupt priority bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 19. interrupt dedicated instruction set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 20. interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 21. eicr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 22. interrupt sensitivity - ei2 (port b3..0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 23. interrupt sensitivity - ei3 (port b7..4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 24. interrupt sensitivity - ei0 (port a3..0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 25. interrupt sensitivity - ei1 (port f2..0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 26. nested interrupts register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 27. mcc/rtc low power mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 28. i/o output mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 29. i/o port mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 30. i/o port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 31. i/o port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 32. effect of low power modes on i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 table 33. i/o port interrupt cont rol/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 table 34. i/o port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 35. effect of low power modes on wdg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 36. wdgcr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 37. watchdog timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 38. effect of low power modes on mcc/rtc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 39. mcc/rtc interrupt control/wake-u p capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 40. mccsr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 41. time base selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 42. mccbcr register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 43. beep frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 44. main clock controller register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 45. artcsr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 46. prescaler selection for art . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 47. artcar register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 48. artaar register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
st72321xx-auto list of tables doc id 13829 rev 1 13/243 table 49. pwm frequency versus resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 50. pwmcr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 51. pwm output signal polarity selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 52. pwmdcrx register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 53. articcsr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 54. articrx register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 55. pwm auto-reload timer register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 56. effect of low power modes on 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 57. 16-bit timer interrupt control/wa ke-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 58. timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 59. cr1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 60. cr2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 61. timer clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 62. csr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 63. 16-bit timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 64. effect of low power modes on spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 30 table 65. spi interrupt control/ wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 0 table 66. spicr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 67. spi master mode sck frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table 68. spicsr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table 69. spi register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 70. frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 table 71. effect of low power modes on sci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 46 table 72. sci interrupt c ontrol/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 table 73. scisr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 table 74. scicr1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 table 75. scicr2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 table 76. scibrr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 77. scierpr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 78. scietpr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 79. baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 80. sci register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 54 table 81. effect of low power modes on i2c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 63 table 82. i2c interrupt co ntrol/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 63 table 83. cr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 table 84. sr1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 table 85. sr2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 86. ccr register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 table 87. dr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 88. oar1 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 table 89. oar2 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 table 90. i2c register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 91. effect of low power modes on adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 table 92. adccsr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 table 93. adcdrh register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 94. adcdrl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 table 95. adc register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 table 96. addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 table 97. cpu addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 table 98. inherent instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 table 99. immediate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 table 100. instructions supporting direct, indexed, indirect, and indirect indexed addressing modes 180
list of tables st72321xx-auto 14/243 doc id 13829 rev 1 table 101. available relative direct/indirect instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 table 102. instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 table 103. instruction set overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 table 104. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 table 105. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 table 106. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 table 107. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 table 108. operating conditions with low voltage detector (lvd) . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 table 109. auxiliary voltage dete ctor (avd) thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 table 110. external voltage detector (evd) thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 table 111. current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 table 112. oscillators,pll and lvd current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 table 113. on-chip peripherals current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 table 114. general timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 table 115. external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 table 116. crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 table 117. oscrange selection for typical resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 table 118. rc oscillator characteri stics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 table 119. pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 table 120. ram supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 table 121. dual voltage hdflash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 table 122. ems test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 table 123. emi emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 table 124. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 02 table 125. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 table 126. i/o port pin general characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 table 127. output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 table 128. asynchronous reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 table 129. iccsel/v pp pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 table 130. 8-bit pwm-art auto-reload timer characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 table 131. 16-bit timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 table 132. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 table 133. i 2 c control interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 table 134. scl frequency table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 table 135. 10-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 table 136. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 table 137. 64-pin (14x14) low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . 220 table 138. 64-pin (10x10) low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . 221 table 139. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 table 140. flash option bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 table 141. option byte 0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 table 142. option byte 1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 table 143. package selection (opt7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 table 144. stmicroelectronics development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 table 145. suggested list of socket types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 table 146. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
st72321xx-auto list of figures doc id 13829 rev 1 15/243 list of figures figure 1. device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 2. 64-pin lqfp 14x14 and 10x10 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 3. 44-pin lqfp package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 4. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 5. memory map and sector address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 figure 6. typical icc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 7. cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 8. stack manipulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 9. clock, reset and supply block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 figure 10. pll block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 11. reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 12. reset sequence phases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 13. reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 14. low voltage detector versus reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 15. using the avd to monitor v dd (avds bit = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 16. using the voltage detector to monitor the evd pin (avds bit = 1). . . . . . . . . . . . . . . . . . . 46 figure 17. interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 18. priority decision process flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 19. concurrent interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 20. nested interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 21. external interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 22. power saving mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 23. slow mode clock transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 24. wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 25. active halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 26. active halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 27. halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 28. halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 29. i/o port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 30. interrupt i/o port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 31. watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 32. approximate timeout duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 33. exact timeout duration (t min and t max ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 34. main clock controller (mcc/rtc) block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 35. pwm auto-reload timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 36. output compare control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 37. pwm auto-reload timer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 38. pwm signal from 0% to 100% duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 39. external event detector example (3 counts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 40. input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 41. timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 42. 16-bit read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 figure 43. counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 44. counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 45. counter timing diagram, internal clock divided by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 46. input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 47. input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 48. output compare block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
list of figures st72321xx-auto 16/243 doc id 13829 rev 1 figure 49. output compare timing diagram, ftimer = fcpu/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 50. output compare timing diagram, ftimer = fcpu/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 51. one pulse mode cycle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 52. one pulse mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 09 figure 53. pulse width modulation mode timing example with 2 output compare functions . . . . . . . 110 figure 54. pulse width modulation cycle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1 figure 55. serial peripheral interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 figure 56. single master/single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 figure 57. generic ss timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 58. hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 59. data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 60. clearing the wcol bit (wri te collision flag) software sequence . . . . . . . . . . . . . . . . . . 129 figure 61. single master / multiple slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 figure 62. sci block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 figure 63. word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 figure 64. sci baud rate and extended prescaler block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 figure 65. bit sampling in reception mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 figure 66. i2c bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 figure 67. i2c interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 figure 68. transfer sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 figure 69. interrupt control logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 figure 70. adc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 figure 71. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 figure 72. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 figure 73. f cpu max versus v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 figure 74. typical i dd in run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 figure 75. typical i dd in slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 figure 76. typical i dd in wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 figure 77. typical i dd in slow wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 figure 78. typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 figure 79. typical application with a crystal or ceramic resonator) . . . . . . . . . . . . . . . . . . . . . . . . . . 196 figure 80. typical f osc(rcint) versus t a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 figure 81. integrated pll jitter versus signal frequency(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 figure 82. unused i/o pins configured as input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 figure 83. typical i pu vs v dd with v in =v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 figure 84. typical v ol at v dd = 5v (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 figure 85. typical v ol at v dd = 5v (high-sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 figure 86. typical v oh at v dd = 5v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 figure 87. typical v ol versus v dd (standard). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 figure 88. typical v ol versus v dd (high-sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 figure 89. typical v dd -v oh versus v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 figure 90. reset pin protection when lvd is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 figure 91. reset pin protection when lvd is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 figure 92. two typical applications with iccsel/v pp pin(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 figure 93. spi slave timing diagram with cpha = 0(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 figure 94. spi slave timing diagram with cpha = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 figure 95. spi master timing diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 figure 96. typical application with i 2 c bus and timing diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . 215 figure 97. r ain maximum versus f adc with c ain = 0pf(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 figure 98. recommended c ain and r ain values(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 figure 99. typical a/d converter application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 figure 100. power supply filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
st72321xx-auto list of figures doc id 13829 rev 1 17/243 figure 101. adc error classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 figure 102. 64-pin (14x14) low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 figure 103. 64-pin (10x10) low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 figure 104. pin 1 orientation in tape and reel conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2 figure 105. st72f321xxx-auto fl ash commercial product structure . . . . . . . . . . . . . . . . . . . . . . . . . 226 figure 106. st72p321xxx-auto fastrom commercial product structure . . . . . . . . . . . . . . . . . . . . . . 228 figure 107. st72321xxx-auto rom commercial product structure. . . . . . . . . . . . . . . . . . . . . . . . . . . 229 figure 108. lvd startup behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
description st72321xx-auto 18/243 doc id 13829 rev 1 1 description the st72321xx-auto flash and rom devices are members of the st7 microcontroller family designed for mid-range automotive applications running from 3.8 to 5.5v. all devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set and are available with flash program memory. the st7 family architecture offers both power and flexib ility to software developers, enabling the design of highly efficient and compact application code. the on-chip peripherals include an a/d converter, a pwm autoreload timer, two general purpose timers, i 2 c, spi, sci interfaces. for power economy, the microcontroller can switch dynamically into wait, slow, active halt or halt mode when the applicatio n is in idle or standby state. typical applications include all types of car body applications such as window lift, dc motor control, rain sensors safety microcontroller in airbag and engine management applications auxiliary functions in car radios table 2. product overview reference program memory ram (stack) voltage range temp. range package st72321r9-auto 60 kbytes flash/rom 2048 (256) bytes 3.8v to 5.5v up to -40c to 125c lqfp64 14x14 ST72321AR9-AUTO lqfp64 10x10 st72321j9-auto lqfp48 10x10 st72321r7-auto 48 kbytes flash/rom 1536 (256) byte lqfp64 14x14 st72321ar7-auto lqfp64 10x10 st72321j7-auto lqfp48 10x10 st72321r6-auto 32 kbytes flash/rom 1024 (256) byte lqfp64 14x14 st72321ar6-auto lqfp64 10x10
st72321xx-auto description doc id 13829 rev 1 19/243 figure 1. device block diagram 8-bit core alu address and data bus osc1 v pp control program (32 or 60 kbytes) v dd reset port f pf7:0 (8-bits) timer a beep port a ram (1024 or 2048 bytes) port c 10-bit adc v aref v ssa port b pb7:0 (8-bits) pwm art port e pe7:0 (8-bits) sci timer b pa 7 : 0 (8-bits) port d pd7:0 (8-bits) spi pc7:0 (8-bits) v ss watchdog tli osc lv d osc2 memory mcc/rtc/beep evd avd i2c
package pinout and pin description st72321xx-auto 20/243 doc id 13829 rev 1 2 package pinout and pin description 2.1 package pinout figure 2. 64-pin lqfp 14x14 and 10x10 package pinout for external pin connection guidelines, refer to section 19: electrical characteristics . v aref v ssa v dd_3 v ss_3 mco / ain8 / pf0 beep / (hs) pf1 (hs) pf2 ocmp2_a / ain9 / pf3 ocmp1_a / ain10 / pf4 icap2_a / ain11 / pf5 icap1_a / (hs) pf6 extclk_a / (hs) pf7 ain4 / pd4 ain5 / pd5 ain6 / pd6 ain7 / pd7 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ei2 ei3 ei0 ei1 pwm3 / pb0 pwm2 / pb1 pwm1 / pb2 pwm0 / pb3 artclk / (hs) pb4 artic1 / pb5 artic2 / pb6 pb7 ain0 / pd0 ain1 / pd1 ain2 / pd2 ain3 / pd3 (hs) pe4 (hs) pe5 (hs) pe6 (hs) pe7 pa 1 pa 0 pc7 / ss / ain15 pc6 / sck / iccclk pc5 / mosi / ain14 pc4 / miso / iccdata pc3 (hs) / icap1_b pc2 (hs) / icap2_b pc1 / ocmp1_b / ain13 pc0 / ocmp2_b / ain12 v ss_0 v dd_0 v ss_1 v dd_1 pa 3 ( h s ) pa 2 v dd _ 2 osc1 osc2 v ss _ 2 tli evd reset v pp / iccsel pa7 (hs) / scli pa 6 ( h s ) / sdai pa 5 ( h s ) pa 4 ( h s ) pe3 pe2 pe1 / rdi pe0 / tdo (hs) 20ma high sink capability eix associated external interrupt vector
st72321xx-auto package pinout and pin description doc id 13829 rev 1 21/243 figure 3. 44-pin lqfp package pinout mco / ain8 / pf0 beep / (hs) pf1 (hs) pf2 ocmp1_a / ain10 / pf4 icap1_a / (hs) pf6 extclk_a / (hs) pf7 v dd_0 v ss_0 ain5 / pd5 v aref v ssa 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 ei2 ei3 ei0 ei1 pwm0 / pb3 artclk / (hs) pb4 ain0 / pd0 ain1 / pd1 ain2 / pd2 ain3 / pd3 ain4 / pd4 rdi / pe1 pwm3 / pb0 pwm2 / pb1 pwm1 / pb2 pc6 / sck / iccclk pc5 / mosi / ain14 pc4 / miso / iccdata pc3 (hs) / icap1_b pc2 (hs) / icap2_b pc1 / ocmp1_b / ain13 pc0 / ocmp2_b / ain12 v ss_1 v dd_1 pa 3 ( h s ) pc7 / ss / ain15 v ss _2 reset v pp / iccsel pa7 (hs) / scli pa6 (hs) / sdai pa 5 ( h s ) pa 4 ( h s ) pe0 / tdo v dd _2 osc1 osc2 (hs) 20ma high sink capability eix associated external interrupt vector
package pinout and pin description st72321xx-auto 22/243 doc id 13829 rev 1 2.2 pin description in the device pin description table, the reset configuration of each pin is shown in bold. this configuration is valid as long as the device is in reset state. refer to section 9: i/o ports on page 70 for more details on the software configuration of the i/o ports. table 3. device pin description pin no. pin name type level port main function (after reset) alternate function lqfp64 lqfp44 input output input output float wpu int ana od pp 1 - pe4(hs) i/o c t hs x xxxport e4 2 - pe5(hs) i/o c t hs x xxxport e5 3 - pe6(hs) i/o c t hs x xxxport e6 4 - pe7(hs) i/o c t hs x xxxport e7 5 2 pb0/pwm3 i/o c t x ei2 x x port b0 pwm output 3 6 3 pb1/pwm2 i/o c t x ei2 x x port b1 pwm output 2 7 4 pb2/pwm1 i/o c t x ei2 x x port b2 pwm output 1 8 5 pb3/pwm0 i/o c t x ei2 x x port b3 pwm output 0 9 6 pb4(hs)/artclk i/o c t hs x ei3 x x port b4 pwm-art external clock 10 - pb5 / artic1 i/o c t x ei3 x x port b5 pwm-art input capture 1 11 - pb6 / artic2 i/o c t x ei3 x x port b6 pwm-art input capture 2 12 - pb7 i/o c t x ei3 x x port b7 13 7 pd0/ain0 i/o c t x x x x x port d0 adc analog input 0 14 8 pd1/ain1 i/o c t x x x x x port d1 adc analog input 1 15 9 pd2/ain2 i/o c t x x x x x port d2 adc analog input 2 16 10 pd3/ain3 i/o c t x x x x x port d3 adc analog input 3 17 11 pd4/ain4 i/o c t x x x x x port d4 adc analog input 4 18 12 pd5/ain5 i/o c t x x x x x port d5 adc analog input 5 19 - pd6/ain6 i/o c t x x x x x port d6 adc analog input 6 20 - pd7/ain7 i/o c t x x x x x port d7 adc analog input 7 21 13 v aref (1) i analog reference voltage for adc 22 14 v ssa (1) s analog ground voltage 23 - v dd_3 (1) s digital main supply voltage 24 - v ss_3 (1) s digital ground voltage
st72321xx-auto package pinout and pin description doc id 13829 rev 1 23/243 25 15 pf0/mco/ain8 i/o c t x ei1 x x x port f0 main clock out (f osc /2) adc analog input 8 26 16 pf1 (hs)/beep i/o c t hs x ei1 x x port f1 beep signal output 27 17 pf2 (hs) i/o c t hs x ei1 x x port f2 28 - pf3/ocmp2_a/ ain9 i/o c t x xxxxport f3 timer a output compare 2 adc analog input 9 29 18 pf4/ocmp1_a/ ain10 i/o c t x xxxxport f4 timer a output compare 1 adc analog input 10 30 - pf5/icap2_a/ ain11 i/o c t x xxxxport f5 timer a input capture 2 adc analog input 11 31 19 pf6(hs)/icap1_a i/o c t hs x x x x port f6 timer a input capture 1 32 20 pf7(hs)/ extclk_a i/o c t hs x xxxport f7 timer a external clock source 33 21 v dd_0 (1) s digital main supply voltage 34 22 v ss_0 (1) s digital ground voltage 35 23 pc0/ocmp2_b/ ain12 i/o c t x xxxxport c0 timer b output compare 2 adc analog input 12 36 24 pc1/ocmp1_b/ ain13 i/o c t x xxxxport c1 timer b output compare 1 adc analog input 13 37 25 pc2(hs)/ icap2_b i/o c t hs x x x x port c2 timer b input capture 2 38 26 pc3(hs)/ icap1_b i/o c t hs x x x x port c3 timer b input capture 1 39 27 pc4/miso/ iccdata i/o c t x xxxport c4 spi master in / slave out data icc data input 40 28 pc5/mosi/ain14 i/o c t x xxxxport c5 spi master out / slave in data adc analog input 14 table 3. device pin description (continued) pin no. pin name type level port main function (after reset) alternate function lqfp64 lqfp44 input output input output float wpu int ana od pp
package pinout and pin description st72321xx-auto 24/243 doc id 13829 rev 1 41 29 pc6/sck/iccclk i/o c t x xxxport c6 spi serial clock icc clock output caution: negative current injection not allowed on this pin (flash devices only) 42 30 pc7/ss /ain15 i/o c t x xxxxport c7 spi slave select (active low) adc analog input 15 43 - pa0 i/o c t x ei0 x x port a0 44 - pa1 i/o c t x ei0 x x port a1 45 - pa2 i/o c t x ei0 x x port a2 46 31 pa3(hs) i/o c t hs x ei0 x x port a3 47 32 v dd_1 (1) s digital main supply voltage 48 33 v ss_1 (1) s digital ground voltage 49 34 pa4(hs) i/o c t hs x xxxport a4 50 35 pa5(hs) i/o c t hs x xxxport a5 51 36 pa6(hs)/sdai i/o c t hs x t port a6 i 2 c data 52 37 pa7(hs)/scli i/o c t hs x t port a7 i 2 c clock 53 38 v pp / iccsel i must be tied low. in flash programming mode, this pin acts as the programming voltage input v pp . see section 19.9.2: iccsel/vpp pin for more details. high voltage must not be applied to rom devices. 54 39 reset i/o c t top priority non-maskable interrupt 55 - evd i a external voltage detector 56 - tli i c t x top level interrupt input pin 57 40 v ss_2 (1) s digital ground voltage 58 41 osc2 (2) i/o resonator oscillator inverter output 59 42 osc1 (2) i external clock input or resonator oscillator inverter input 60 43 v dd_2 (1) s digital main supply voltage 61 44 pe0/tdo i/o c t x x x x port e0 sci transmit data out 62 1 pe1/rdi i/o c t x x x x port e1 sci receive data in table 3. device pin description (continued) pin no. pin name type level port main function (after reset) alternate function lqfp64 lqfp44 input output input output float wpu int ana od pp
st72321xx-auto package pinout and pin description doc id 13829 rev 1 25/243 legend / abbreviations for ta b l e 3 : type: i = input o = output s = supply input level: a = dedicated analog input in/output level: c = cmos 0.3v dd /0.7v dd c t = cmos 0.3v dd /0.7v dd with input trigger output level: hs = 20ma high sink (on n-buffer only) port and control configuration: input: float = floating wpu = weak pull-up int = interrupt (a) ana = analog output: od = open-drain (b) pp = push-pull 63 - pe2 (flash device) i/o c t x port e2 caution: in flash devices this port is always input with weak pull-up. pe2 (rom device) x xx port e2 caution: in rom devices, no weak pull-up present on this port. in lqfp44 this pin is not connected to an internal pull-up like other unbonded pins. it is recommended to configure it as output push-pull to avoid added current consumption. 64 - pe3 i/o c t x xxxport e3 1. it is mandatory to connect all available v dd and v aref pins to the supply voltage and all v ss and v ssa pins to ground. 2. osc1 and osc2 pins connect a crystal/ceramic resonator or an external source to the on-chip oscillator; see section 6: supply, reset and clock management and section 19.5: clock and timi ng characteristics on page 195 for more details. table 3. device pin description (continued) pin no. pin name type level port main function (after reset) alternate function lqfp64 lqfp44 input output input output float wpu int ana od pp a. in the interrupt input column, ?eix? defines the associ ated external interrupt vector. if the weak pull-up column (wpu) is merged with the interrupt column (int), then t he i/o configuration is pull-up interrupt input, otherwise the configuration is floating interrupt input. b. in the open-drain output column, ?t? defines a tr ue open-drain i/o (p-buffer and protection diode to v dd are not implemented). see section 9: i/o ports on page 70 and section 19.8: i/o port pi n characteristics on page 203 for more details.
register and memory map st72321xx-auto 26/243 doc id 13829 rev 1 3 register and memory map as shown in figure 4 , the mcu is capable of addressing 64 kbytes of memories and i/o registers. the available memory locations consist of 128 bytes of register locations, up to 2 kbytes of ram and up to 60 kbytes of user program memory. the ram space includes up to 256 bytes for the stack from 0100h to 01ffh. the highest address bytes contain the user reset and interrupt vectors. important: memory locations marked as ?reserved? must never be accessed. accessing a reserved area can have unpredictable effects on the device. related documentation executing code in st7 ram ( an 985) figure 4. memory map 0000h ram program memory (60k or 32k) interrupt & reset vectors hw registers 0080h 007fh 0fffh (see ta b l e 4 ) 1000h ffdfh ffe0h ffffh (see ta b l e 2 0 ) 0880h reserved 087fh short addressing ram (zero page) 256 bytes stack 16-bit addressing ram 0100h 01ffh 0080h 0200h 00ffh or 087fh 32 kbytes 8000h 60 kbytes ffffh 1000h (2048 or 1024 bytes) or 067fh or 047fh table 4. hardware register map address block register label register name reset status remarks 0000h 0001h 0002h port a pa d r pa d d r pao r port a data register port a data direction register port a option register 00h (1) 00h 00h r/w r/w r/w 0003h 0004h 0005h port b pbdr pbddr pbor port b data register port b data direction register port b option register 00h (1) 00h 00h r/w r/w r/w 0006h 0007h 0008h port c pcdr pcddr pcor port c data register port c data direction register port c option register 00h (1) 00h 00h r/w r/w r/w 0009h 000ah 000bh port d pddr pdddr pdor port d data register port d data direction register port d option register 00h (1) 00h 00h r/w r/w r/w
st72321xx-auto register and memory map doc id 13829 rev 1 27/243 000ch 000dh 000eh port e pedr peddr peor port e data register port e data direction register port e option register 00h (1) 00h 00h r/w r/w (2) r/w (2) 000fh 0010h 0011h port f pfdr pfddr pfor port f data register port f data direction register port f option register 00h (1) 00h 00h r/w r/w r/w 0018h 0019h 001ah 001bh 001ch 001dh 001eh i 2 c i2ccr i2csr1 i2csr2 i2cccr i2coar1 i2coar2 i2cdr i 2 c control register i 2 c status register 1 i 2 c status register 2 i 2 c clock control register i 2 c own address register 1 i 2 c own address register2 i 2 c data register 00h 00h 00h 00h 00h 00h 00h r/w read only read only r/w r/w r/w r/w 001fh 0020h reserved area (2 bytes) 0021h 0022h 0023h spi spidr spicr spicsr spi data i/o register spi control register spi control/status register xxh 0xh 00h r/w r/w r/w 0024h 0025h 0026h 0027h itc ispr0 ispr1 ispr2 ispr3 interrupt software priority register 0 interrupt software priority register 1 interrupt software priority register 2 interrupt software priority register 3 ffh ffh ffh ffh r/w r/w r/w r/w 0028h eicr external interrupt control register 00h r/w 0029h flash fcsr flash control/status register 00h r/w 002ah watchdog wdgcr watchdog control register 7fh r/w 002bh sicsr system integrity control/status register 000x 000x b r/w 002ch 002dh mcc mccsr mccbcr main clock control / status register main clock controller: beep control register 00h 00h r/w r/w 002eh to 0030h reserved area (3 bytes) 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003ah 003bh 003ch 003dh 003eh 003fh timer a tacr2 tacr1 tac s r ta i c 1 h r taic1lr tao c 1 h r tao c 1 l r tachr tac l r ta ac h r ta ac l r ta i c 2 h r taic2lr tao c 2 h r tao c 2 l r timer a control register 2 timer a control register 1 timer a control/status register timer a input capture 1 high register timer a input capture 1 low register timer a output compare 1 high register timer a output compare 1 low register timer a counter high register timer a counter low register timer a alternate counter high register timer a alternate counter low register timer a input capture 2 high register timer a input capture 2 low register timer a output compare 2 high register timer a output compare 2 low register 00h 00h xxxx x0xx b xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w r/w read only read only r/w r/w read only read only read only read only read only read only r/w r/w table 4. hardware register map (continued) address block register label register name reset status remarks
register and memory map st72321xx-auto 28/243 doc id 13829 rev 1 note: legend: x = undefined, r/w = read/write 0040h reserved area (1 byte) 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004ah 004bh 004ch 004dh 004eh 004fh timer b tbcr2 tbcr1 tbcsr tbic1hr tbic1lr tboc1hr tboc1lr tbchr tbclr tbachr tbaclr tbic2hr tbic2lr tboc2hr tboc2lr timer b control register 2 timer b control register 1 timer b control/status register timer b input capture 1 high register timer b input capture 1 low register timer b output compare 1 high register timer b output compare 1 low register timer b counter high register timer b counter low register timer b alternate counter high register timer b alternate counter low register timer b input capture 2 high register timer b input capture 2 low register timer b output compare 2 high register timer b output compare 2 low register 00h 00h xxxx x0xx b xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w r/w read only read only r/w r/w read only read only read only read only read only read only r/w r/w 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h sci scisr scidr scibrr scicr1 scicr2 scierpr scietpr sci status register sci data register sci baud rate register sci control register 1 sci control register 2 sci extended receive prescaler register reserved area sci extended transmit prescaler register c0h xxh 00h x000 0000b 00h 00h --- 00h read only r/w r/w r/w r/w r/w r/w 0058h 006fh reserved area (24 bytes) 0070h 0071h 0072h adc adccsr adcdrh adcdrl control/status register data high register data low register 00h 00h 00h r/w read only read only 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007ah 007bh 007ch 007dh pwm art pwmdcr3 pwmdcr2 pwmdcr1 pwmdcr0 pwmcr artcsr artcar artarr articcsr articr1 articr2 pwm ar timer duty cycle register 3 pwm ar timer duty cycle register 2 pwm ar timer duty cycle register 1 pwm ar timer duty cycle register 0 pwm ar timer control register auto-reload timer control/status register auto-reload timer counter access register auto-reload timer auto-reload register ar timer input capture control/status reg. ar timer input capture register 1 ar timer input capture register 1 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h r/w r/w r/w r/w r/w r/w r/w r/w r/w read only read only 007eh 007fh reserved area (2 bytes) 1. the contents of the i/o port dr registers are readable only in out put configuration. in input c onfiguration, the values of th e i/o pins are returned instead of the dr register contents. 2. the bits associated with unavailable pi ns must always keep their reset value. table 4. hardware register map (continued) address block register label register name reset status remarks
st72321xx-auto flash program memory doc id 13829 rev 1 29/243 4 flash program memory 4.1 introduction the st7 dual voltage high density flash (hdflash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a byte-by- byte basis using an external v pp supply. the hdflash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using icp (in-circuit programming) or iap (in-application programming). the array matrix organization allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 main features 3 flash programming modes: ? insertion in a programming tool. in this mode, all sectors including option bytes can be programmed or erased. ? icp (in-circuit programming). in this mode, all sectors including option bytes can be programmed or erased without removing the device from the application board. ? iap (in-application programming). in this mode, all sectors except sector 0 can be programmed or erased without removing the device from the application board and while the application is running. ict (in-circuit testing) for downloading and executing user application test patterns in ram readout protection register access security system (rass) to prevent accidental programming or erasing 4.3 structure the flash memory is organized in sectors and can be used for both code and data storage. depending on the overall flash memory size in the microcontroller device, there are up to three user sectors (see ta b l e 5 ). each of these sectors can be erased independently to avoid unnecessary erasing of the whole flas h memory when only a partial erasing is required. the first two sectors have a fixed size of 4 kbytes (see figure 5 ). they are mapped in the upper part of the st7 addressing space so the reset and interrupt vectors are located in sector 0 (f000h-ffffh). table 5. sectors available in flash devices flash size (bytes) available sectors 4k sector 0 8k sectors 0, 1 > 8k sectors 0, 1, 2
flash program me mory st72321xx-auto 30/243 doc id 13829 rev 1 figure 5. memory map and sector address 4.3.1 readout protection readout protection, when selected, provides a protection against program memory content extraction and against write access to flash memory. even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. in flash devices, this protection is removed by reprogramming the option. in this case, the entire program memory is first automatically erased and the device can be reprogrammed. note: 4.4 icc interface icc needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see figure 6 ). these pins are: reset : device reset v ss : device power supply ground iccclk: icc output serial clock pin iccdata: icc input/output serial data pin iccsel/v pp : programming voltage osc1 (or oscin): main clock input for external source (optional) v dd : application board power supply (optional, see figure 6 , note 3 ) 4 kbytes 4 kbytes 2kbytes sector 1 sector 0 16 kbytes sector 2 8k 16k 32k 60k flash ffffh efffh dfffh 3fffh 7fffh 1000h 24 kbytes memory size 8kbytes 40 kbytes 52 kbytes 9fffh bfffh d7ffh 4k 10k 24k 48k
st72321xx-auto flash program memory doc id 13829 rev 1 31/243 figure 6. typical icc interface 1. if the iccclk or iccdata pins are only used as outputs in the application, no signal isolation is necessary. as soon as the programming tool is plugged to the board, even if an icc sess ion is not in progress, the iccclk and iccdata pins are not available for the application. if they ar e used as inputs by the appl ication, isolation such as a serial resistor has to implemented in case another device forces the signal. re fer to the programming tool documentation for recommended resistor values. 2. during the icc session, the programming tool must control the reset pin. this can lead to conflicts between the programming tool and the application reset ci rcuit if it drives more than 5ma at high level (push-pull output or pull-up resistor < 1k). a schottky diode can be used to isolate the applic ation reset circuit in this case. when using a classical rc network with r > 1k or a reset management ic with open-drain output and pull-up resistor > 1k, no additional components are needed. in all cases the user must ensure that no external reset is generated by the application during the icc session. 3. the use of pin 7 of the icc connector depends on the progr amming tool architecture. this pin must be connected when using most st programming tools (it is used to monitor the application power suppl y). please refer to the programming tool manual. 4. pin 9 has to be connected to the osc1 or oscin pin of the st 7 when the clock is not availabl e in the application or if the selected clock option is not programmed in the option byte. st 7 devices with multi-oscillato r capability need to have osc2 grounded in this case. 4.5 icp (in-circuit programming) to perform icp the microcontroller must be switched to icc (in-circuit communication) mode by an external controller or programming tool. depending on the icp code downloaded in ram, flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading). when using an stmicroelectronics or third-party programming tool that supports icp and the specific microcontroller device, the user needs only to implement the icp hardware interface on the application board (see figure 6 ). for more details on the pin locations, refer to the device pinout description. icc connector iccdata iccclk reset v dd he10 connector type application power supply 1 2 4 6 8 10 97 5 3 programming tool icc connector application board icc cable (see note 3) 10k ? v ss iccsel/vpp st7 c l2 c l1 osc1 osc2 optional see note 1 see note 2 application reset source application i/o (see note 4)
flash program me mory st72321xx-auto 32/243 doc id 13829 rev 1 4.6 iap (in-application programming) this mode uses a bootloader program previously stored in sector 0 by the user (in icp mode or by plugging the device in a programming tool). this mode is fully controlled by user software. this allows it to be adapted to the user application, (such as user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored). for example, it is possible to download code from the interface and program it in the flash. iap mode can be used to program any of the flash sectors except sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation. 4.7 related documentation for details on flash programming and icc protocol, refer to the st7 flash programming reference manual and to the st7 icc protocol reference manual . 4.8 flash control/status register (fcsr) this register is reserved for use by programming tool software. it controls the flash programming and erasing operations. fscr reset value: 0000 0000 (00h) 76543210 00000000 rw rw rw rw rw rw rw rw table 6. flash control/status register address and reset value address (hex.) register label 7 6 5 4 3 2 1 0 0029h fcsr reset value 00000000
st72321xx-auto central processing unit (cpu) doc id 13829 rev 1 33/243 5 central processing unit (cpu) 5.1 introduction this cpu has a full 8-bit architecture and contains six internal registers allowing efficient 8- bit data manipulation. 5.2 main features enable executing 63 basic instructions fast 8-bit by 8-bit multiply 17 main addressing modes (with indirect addressing mode) two 8-bit index registers 16-bit stack pointer low power halt and wait modes priority maskable hardware interrupts non-maskable software/hardware interrupts 5.3 cpu registers the six cpu registers shown in figure 7 are not present in the memory mapping and are accessed by specific instructions. figure 7. cpu registers accumulator x index register y index register stack pointer condition code register program counter 70 1c 1i1hi0nz reset value = reset vector @ fffeh-ffffh 70 70 70 0 7 15 8 pch pcl 15 8 7 0 reset value = stack higher address reset value = 1 x 11x1xx reset value = xxh reset value = xxh reset value = xxh x = undefined value
central processing unit (cpu) st72321xx-auto 34/243 doc id 13829 rev 1 5.3.1 accumulator (a) the accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations as well as data manipulations. 5.3.2 index registers (x and y) these 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation (the cross-assembler generates a precede instruction (pre) to indicate that the following instruction refers to the y register.) the y register is not affected by the interrupt automatic procedures. 5.3.3 program counter (pc) the program counter is a 16-bit register containing the address of the next instruction to be executed by the cpu. it is made of two 8-bit registers pcl (program counter low which is the lsb) and pch (program counter high which is the msb). 5.3.4 condition code (cc) register the 8-bit condition code register contains the interrupt masks and four flags representative of the result of the instruction just executed. this register can also be handled by the push and pop instructions. these bits can be individually tested and/or controlled by specific instructions. cc reset value: 111x1xxx 76543210 11i1hi0nzc rw rw rw rw rw rw table 7. arithmetic management bits bit name function 4 h half carry this bit is set by hardware when a carry occurs between bits 3 and 4 of the alu during an add or adc instructions. it is reset by hardware during the same instructions. 0: no half carry has occurred. 1: a half carry has occurred. this bit is tested using the jrh or jrnh in struction. the h bit is useful in bcd arithmetic subroutines. 2n negative this bit is set and cleared by hardware. it is representative of the result sign of the last arithmetic, logical or data manipulati on. it is a copy of the result 7th bit. 0: the result of the last operation is positive or null. 1: the result of the last oper ation is negative (that is, the most significant bit is a logic 1). this bit is accessed by the jrmi and jrpl instructions.
st72321xx-auto central processing unit (cpu) doc id 13829 rev 1 35/243 these two bits are set/cleared by hardware when entering in interrupt. the loaded value is given by the corresponding bits in the interrupt software priority registers (isprx). they can be also set/cleared by software with the rim, sim, iret, halt, wfi and push/pop instructions. see chapter 7: interrupts on page 49 for more details. 5.3.5 stack pointer (sp) register 7 1z zero this bit is set and cleared by hardware. this bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: the result of the last oper ation is different from zero. 1: the result of the last operation is zero. this bit is accessed by the jreq and jrne test instructions. 0 c carry/borrow this bit is set and cleared by hardware and software. it indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: no overflow or underflow has occurred. 1: an overflow or underflow has occurred. this bit is driven by the scf and rcf instructions and tested by the jrc and jrnc instructions. it is also affected by the ?bit test and branch?, shift and rotate instructions. table 8. interrupt management bits bit name function 5 i1 interrupt software priority 1 the combination of the i1 and i0 bits gives the current interrupt software priority. 3 i0 interrupt software priority 0 the combination of the i1 and i0 bits gives the current interrupt software priority. table 9. interrupt software priority selection interrupt software priority level i1 i0 level 0 (main) low high 10 level 1 01 level 2 00 level 3 (= interrupt disable) 1 1 table 7. arithmetic management bits (continued) bit name function sp reset value: 01 ffh 1514131211109876543210 00000001sp7sp6sp5sp4sp3sp2sp1sp0 rw rw rw rw rw rw rw rw
central processing unit (cpu) st72321xx-auto 36/243 doc id 13829 rev 1 the stack pointer is a 16-bit register which is always pointing to the next free location in the stack. it is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see figure 8 ). since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware. following an mcu reset, or after a reset stack pointer instruction (rsp), the stack pointer contains its reset value (the sp7 to sp0 bits are set) which is the stack higher address. the least significant byte of the stack pointer (called s) can be directly accessed by an ld instruction. note: when the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, without indicating the stack overflow. the previously stored information is then overwritten and therefore lost. the stack also wraps in case of an underflow. the stack is used to save the return address during a subroutine call and the cpu context during an interrupt. the user may also directly manipulate the stack by means of the push and pop instructions. in the case of an interrupt, the pcl is stored at the first location pointed to by the sp. the other registers are then stored in the next locations as shown in figure 8 . when an interrupt is received, the sp is decremented and the context is pushed on the stack. on return from interrupt, the sp is incremented and the context is popped from the stack. a subroutine call occupies two locations and an interrupt five locations in the stack area. figure 8. stack manipulation example pch pcl sp pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp sp y call subroutine interrupt event push y pop y iret ret or rsp @ 01ffh @ 0100h stack higher address = 01ffh stack lower address = 0100h
st72321xx-auto supply, reset and clock management doc id 13829 rev 1 37/243 6 supply, reset and clock management 6.1 introduction the device includes a range of utility featur es for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. an overview is shown in figure 9 . for more details, refer to the dedicated parametric section. 6.2 main features optional pll for multiplying the frequency by 2 (not to be used with internal rc oscillator) reset sequence manager (rsm) multi-oscillator clock management (mo) ? 5 crystal/ceramic resonator oscillators ? 1 internal rc oscillator system integrity management (si) ? main supply low voltage detection (lvd) ? auxiliary voltage detector (avd) with interr upt capability for mo nitoring the main supply or the evd pin figure 9. clock, reset and supply block diagram low voltage detector (lvd) f osc2 auxiliary voltage detector (avd) multi- oscillator (mo) osc1 reset v ss evd v dd reset sequence manager (rsm) osc2 main clock avd interrupt request controller pll system integrity management watchdog sicsr timer (wdg) with real-time clock (mcc/rtc) avd avd avd lv d rf ie wdg rf 0 1 f osc (option) 0 s f f cpu 00
supply, reset and clock management st72321xx-auto 38/243 doc id 13829 rev 1 6.3 phase locked loop if the clock frequency input to the pll is in the range 2 to 4 mhz, the pll can be used to multiply the frequency by two to obtain an f osc2 of 4 to 8 mhz. the pll is enabled by option byte. if the pll is disabled, then f osc2 =f osc /2. caution: the pll is not recommended for applications where timing accuracy is required (see section 19.5.5: pll characteristics on page 198 ). figure 10. pll block diagram 6.4 multi-oscillator (mo) the main clock of the st7 can be generated by three different source types coming from the multi-oscillator block: an external source 4 crystal or ceramic resonator oscillators an internal high fr equency rc oscillator each oscillator is optimized fo r a given frequency range in terms of consumption and is selectable through the option byte. the associated hardware configurations are shown in table 10 . refer to section 19: electrical characteristics for more details. caution: the osc1 and/or osc2 pins must not be left unconnected. for the purposes of failure mode and effect analysis, it should be noted that if the osc1 and/or osc2 pins are left unconnected, the st7 main oscillator may start a nd, in this configuration, could generate an f osc clock frequency in excess of the allowed maximum (> 16 mhz), putting the st7 in an unsafe/undefined state. the product behavior must therefore be considered undefined when the osc pins are left unconnected. external clock source in this external clock mode, a clock signal (s quare, sinus or triangle) with ~50% duty cycle has to drive the osc1 pin while the osc2 pin is tied to ground. 0 1 pll option bit pll x 2 f osc2 / 2 f osc
st72321xx-auto supply, reset and clock management doc id 13829 rev 1 39/243 crystal/ceramic oscillators this family of oscillators has the advantage of prod ucing a very accurate rate on the main clock of the st7. the selection within a list of four oscillators with diff erent frequency ranges has to be done by option byte in order to reduce consumption (refer to section 21.1.1: flash configuration on page 223 for more details on the frequency ranges). in this mode of the multi-oscillator, the resonator a nd the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize ou tput distortion and star t-up stabilization time. the loading capacitance values must be adj usted according to t he selected oscillator. these oscillators are not stopped during the reset phase to avoid losing time in the oscillator start-up phase. internal rc oscillator this oscillator allows a low cost solution for the main clock of the st7 using only an internal resistor and capacitor. internal rc oscillato r mode has the drawback of a lower frequency accuracy and should not be used in applications that require accurate timing. in this mode, the two oscillator pins have to be tied to ground. table 10. st7 clock sources hardware configuration external clock crystal/ceramic resonators internal rc oscillator osc1 osc2 external st7 source osc1 osc2 load capacitors st7 c l2 c l1 osc1 osc2 st7
supply, reset and clock management st72321xx-auto 40/243 doc id 13829 rev 1 6.5 reset sequence manager (rsm) 6.5.1 introduction the reset sequence manager includes three reset sources as shown in figure 11 : external reset source pulse internal lvd reset (low voltage detection) internal watchdog reset these sources act on the reset pin and it is always kept low during the delay phase. the reset service routine vector is fixed at addresses fffeh-ffffh in the st7 memory map. the basic reset sequence consists of three phases as shown in figure 12 : active phase depending on the reset source 256 or 4096 cpu clock cycle delay (selected by option byte) reset vector fetch caution: when the st7 is unprogrammed or fully erased, the flash is blank and the reset vector is not programmed. for this reason, it is recommended to keep the reset pin in low state until programming mode is entered, in order to avoid unwanted behavior. the 256 or 4096 cpu clock cycle delay allows the oscillator to stabilize and ensures that recovery has taken place from the reset stat e. the shorter or longer clock cycle delay should be selected by option byte to correspond to the stabilization time of the external oscillator used in the application (see section 21.1.1: flash configuration on page 223 ). the reset vector fetch phase duration is 2 clock cycles. figure 11. reset block diagram reset r on v dd watchdog reset lvd reset internal reset pulse generator filter
st72321xx-auto supply, reset and clock management doc id 13829 rev 1 41/243 figure 12. reset sequence phases 6.5.2 asynchronous external reset pin the reset pin is both an input and an open-drain output with integrated r on weak pull-up resistor. this pull-up has no fixed value but varies in accordance with the input voltage. it can be pulled low by external circuitry to reset the device. see section 19.9: control pin characteristics on page 207 for more details. a reset signal originating from an external source must have a duration of at least t h(rstl)in in order to be recognized (see figure 13 ). this detection is asynchronous and therefore the mcu can enter reset state even in halt mode. the reset pin is an asynchronous sign al which plays a major role in ems performance. in a noisy environment, it is recommended to follow the guidelines mentioned in section 19: electrical characteristics . if the external reset pulse is shorter than t w(rstl)out (see short ext. reset in figure 13 ), the signal on the reset pin may be stretched. otherwise the delay will not be applied (see long ext. reset in figure 13 ). starting from the external reset pulse recognition, the device reset pin acts as an output that is pulled low during at least t w(rstl)out . 6.5.3 external power-on reset if the lvd is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until v dd is over the minimum level specif ied for the selected f osc frequency (see section 19.3: operating conditions on page 188 ). a proper reset signal for a slow rising v dd supply can generally be provided by an external rc network connected to the reset pin. 6.5.4 internal low voltage detector (lvd) reset two different reset sequences ca used by the internal lvd ci rcuitry can be distinguished: power-on reset voltage drop reset the device reset pin acts as an output that is pulled low when v dd supply, reset and clock management st72321xx-auto 42/243 doc id 13829 rev 1 6.5.5 internal watchdog reset the reset sequence generated by an internal watchdog counter overflow is shown in figure 13 . starting from the watchdog co unter underflow, the device reset pin acts as an output that is pulled low during at least t w(rstl)out . figure 13. reset sequences v dd run reset pin external watchdog active phase v it+(lvd) v it-(lvd) t h(rstl)in t w(rstl)out run t h(rstl)in active watchdog underflow t w(rstl)out run run run reset reset source short ext. reset lv d reset long ext. reset watchdog reset internal reset (256 or 4096 t cpu ) vector fetch t w(rstl)out phase active phase active phase delay
st72321xx-auto supply, reset and clock management doc id 13829 rev 1 43/243 6.6 system integrity management (si) the system integrity management block contains the low voltage detector (lvd) and auxiliary voltage detector (avd) functions . it is managed by the sicsr register. 6.6.1 low voltage detector (lvd) the low voltage detector function (lvd) generates a static reset when the v dd supply voltage is below a v it- reference value. this means that it secures the power-up as well as the power-down keeping the st7 in reset. the v it- reference value for a voltage drop is lower than the v it+ reference value for power- on in order to avoid a parasitic reset when the mcu starts running and sinks current on the supply (hysteresis). the lvd reset circuitry generates a reset when v dd is below: ?v it+ when v dd is rising ?v it- when v dd is falling the lvd function is illustrated in figure 14 . the voltage threshold can be configured by option byte to be low, medium or high. provided the minimum v dd value (guaranteed for the osc illator frequency) is above v it- , the mcu can only be in two modes: ? under full software control ? in static safe reset in these conditions, secure operation is always ensured for the application without the need for external reset hardware. during a low voltage detector reset, the reset pin is held low, thus permitting the mcu to reset other devices. note: the lvd allows the device to be us ed without any external reset circuitry. if the medium or low thresholds are selected, the detection may occur outside the specified operating voltage range. below 3.8v, device operation is not guaranteed. the lvd is an optional function which can be selected by option byte. it is recommended to make sure that the v dd supply voltage rises monotonously when the device is exiting from reset, to ensure the application functions properly.
supply, reset and clock management st72321xx-auto 44/243 doc id 13829 rev 1 figure 14. low voltage detector versus reset 6.6.2 auxiliary voltage detector (avd) the auxiliary voltage detector function (avd) is based on an analog compar ison between a v it-(avd) and v it+(avd) reference value and the v dd main supply or the external evd pin voltage level (v evd ). the v it- reference value for falling voltage is lower than the v it+ reference value for rising voltage in order to avoid parasitic detection (hysteresis). the output of the avd comparator can be read directly by the application software through a real-time status bit (avdf) in the sicsr register. this bit is read only. caution: the avd function is active only if the lvd is enabled through the option byte. monitoring the v dd main supply this mode is selected by clearing the avds bit in the sicsr register. the avd voltage threshold value is relative to the selected lvd threshold configured by option byte (see section 21.1.1: flash configuration on page 223 ). if the avd interrupt is enabled, an interrupt is generated when the voltage crosses the v it+(avd) or v it-(avd) threshold (avdf bit toggles). in the case of a drop in voltage, the avd interrupt acts as an early warning, allowing software to shut down safely before the lvd resets the microcontroller. see figure 15 . the interrupt on the rising edge is used to inform the application that the v dd warning state is over. if the voltage rise time t rv is less than 256 or 4096 cpu cycles (depending on the reset delay selected by option byte), no avd interrupt will be generated when v it+(avd) is reached. if t rv is greater than 256 or 4096 cycles two avd interrupts will be received if the avd interrupt is enabled before the v it+(avd) threshold is reached: the first when the avdie bit is set, and the second when the threshold is reached. only one avd interrupt will occur if the avd interrupt is enabled after the v it+(avd) threshold is reached. v dd v it+ reset v it- v hys
st72321xx-auto supply, reset and clock management doc id 13829 rev 1 45/243 figure 15. using the avd to monitor v dd (avds bit = 0) monitoring a voltage on the evd pin this mode is selected by setting the avds bit in the sicsr register. the avd circuitry can generate an interrupt when the avdie bit of the sicsr register is set. this interrupt is gener ated on the rising and falling edges of the comparator output. this means it is generated when either one of these two events occur: v evd rises up to v it+(evd) v evd falls down to v it-(evd) the evd function is illustrated in figure 16 . for more details, refer to section 19: electrical characteristics . v dd v it+(avd) v it-(avd) avdf bit 0 0 reset value if avdie bit = 1 v hyst avd interrupt request interrupt process interrupt process v it+(lvd) v it-(lvd) lvd reset early warning interrupt (power has dropped, mcu not not yet in reset) 1 1 t rv voltage rise time
supply, reset and clock management st72321xx-auto 46/243 doc id 13829 rev 1 figure 16. using the voltage detector to monitor the evd pin (avds bit = 1) 6.6.3 low power modes 6.6.4 interrupts the avd interrupt event generates an interrupt if the corresponding enable control bit (avdie) is set and the interrupt mask in the cc register is reset (rim instruction). v evd v it+(evd) v it-(evd) avdf 0 0 1 if avdie = 1 v hyst avd interrupt request interrupt process interrupt process table 11. effect of low power modes on si mode effect wait no effect on si. avd interrupts cause the device to exit from wait mode. halt the sicsr register is frozen. table 12. avd interrupt control/wake-up capability interrupt event event flag enable control bit exit from wait exit from halt avd event avdf avdie yes no
st72321xx-auto supply, reset and clock management doc id 13829 rev 1 47/243 6.6.5 system integrity (si) control/status register (sicsr) sicsr reset value: 000x 000x (00h) 76543210 avds avdie avdf lvdrf reserved wdgrf rw rw rw rw - rw table 13. sicsr description bit name function 7avds voltage detection selection this bit is set and cleared by software. voltage detection is available only if the lvd is enabled by option byte. 0: voltage detection on v dd supply 1: voltage detection on evd pin 6 avdie voltage detector interrupt enable this bit is set and cleared by software. it enables an interrupt to be generated when the avdf flag changes (toggles). the pending interrupt information is automatically cleared when software enters the avd interrupt routine. 0: avd interrupt disabled 1: avd interrupt enabled 5avdf voltage detector flag this read-only bit is set and cleared by hardware. if the avdie bit is set, an interrupt request is generated when the avdf bit changes value. refer to figure 15 and to monitoring the vdd main supply on page 44 for additional details. 0: v dd or v evd over v it+(avd) threshold 1: v dd or v evd under v it-(avd) threshold 4 lvdrf lvd reset flag this bit indicates that the last reset was generated by the lvd block. it is set by hardware (lvd reset) and cleared by software (writing zero). see table 14: reset source flags for more details. when the lvd is disabled by option byte, the lvdrf bit value is undefined. 3:1 - reserved, must be kept cleared. 0 wdgrf watchdog reset flag this bit indicates that the last reset wa s generated by the watchdog peripheral. it is set by hardware (watchdog reset) and cleared by software (writing zero) or an lvd reset (to ensure a stable cleared st ate of the wdgrf flag when cpu starts). combined with the lvdrf flag information, the flag description is given in ta b l e 1 4 . table 14. reset source flags reset sources lvdrf wdgrf external reset pin 0 0 watchdog 0 1 lv d 1 x
supply, reset and clock management st72321xx-auto 48/243 doc id 13829 rev 1 application notes the lvdrf flag is not cleared when another reset ty pe occurs (external or watchdog); the lvdrf flag remains set to keep trace of the original failure. in this case, software can detect a watchdog reset but cannot detect an external reset. caution: when the lvd is not activated with the associated option byte, the wdgrf flag cannot be used in the application.
st72321xx-auto interrupts doc id 13829 rev 1 49/243 7 interrupts 7.1 introduction the st7 enhanced interrupt management provides the following features: hardware interrupts software interrupt (trap) nested or concurrent interrupt management with flexible interrupt priority and level management: ? up to 4 software programmable nesting levels ? up to 16 interrupt vectors fixed by hardware ? 2 non-maskable events: reset, trap ? 1 maskable top level event: tli this interrupt management is based on: bit 5 and bit 3 of the cpu cc register (i1:0) interrupt software priority registers (isprx) fixed interrupt vector addresses located at the high addresses of the memory map (ffe0h to ffffh) sorted by hardware priority order this enhanced in terrupt controller guarant ees full upward compatib ility with the standard (not nested) st7 interrupt controller. 7.2 masking and processing flow the interrupt masking is managed by the i1 and i0 bits of the cc register and the isprx registers which give the interrupt software priority level of each interrupt vector (see ta bl e 15 ). the processing flow is shown in figure 17 . when an interrupt request has to be serviced: normal processing is suspended at the end of the current instruction execution. the pc, x, a and cc registers are saved onto the stack. i1 and i0 bits of cc register are set according to the corresponding values in the isprx registers of the serviced interrupt vector. the pc is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to table 20: interrupt mapping for vector addresses). the interrupt service routine should end with the iret instruction which causes the contents of the saved registers to be recovered from the stack. note: as a consequence of the iret instruction, th e i1 and i0 bits will be restored from the stack and the program in the pr evious level will resume.
interrupts st72321xx-auto 50/243 doc id 13829 rev 1 figure 17. interrupt processing flowchart servicing pending interrupts as several interrupts can be pending at the same time, the interrupt to be taken into account is determined by the following two-step process: the highest software priority interrupt is serviced, if several interrupts have the same software priority then the interrupt with the highest hardware priority is serviced first. figure 18 describes this decision process. figure 18. priority decision process flowchart table 15. interrupt software priority levels interrupt software priority level i1 i0 level 0 (main) low high 10 level 1 0 1 level 2 0 0 level 3 (= interrupt disable) 1 1 ?iret? restore pc, x, a, cc stack pc, x, a, cc load i1:0 from interrupt sw reg. fetch next reset trap pending instruction i1:0 from stack load pc from interrupt vector y n y n y n interrupt has the same or a lower software priority the interrupt stays pending than current one interrupt has a higher software priority than current one execute instruction interrupt pending software different interrupts same highest hardware priority serviced priority highest software priority serviced
st72321xx-auto interrupts doc id 13829 rev 1 51/243 when an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one. note: 1 the hardware priority is exclusive while the software one is not. this allows the previous process to succeed with only one interrupt. 2 tli, reset and trap can be considered as having the highest software priority in the decision process. different interrupt vector sources two interrupt source types are managed by the st7 interrupt controller: the non-maskable type (reset, trap) and the maskable type (e xternal or from in ternal peripherals). non-maskable sources these sources are processed regardless of the state of the i1 and i0 bits of the cc register (see figure 17 ). after stacking the pc, x, a and cc registers (except for reset), the corresponding vector is loaded in the pc register and the i1 and i0 bits of the cc are set to disable interrupts (level 3). these sources allow the processor to exit halt mode. trap (non-maskable software interrupt) this software interrupt is serviced when the trap instruction is executed. it will be serviced according to the flowchart in figure 17 . caution: trap can be interrupted by a tli. reset the reset source has the highest priority in the st7. this means that the first current routine has the highest software priority (level 3) and the highest hardware priority. see section 6.5: reset sequence manager (rsm) on page 40 for more details. maskable sources maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in isprx registers) is higher than the one currently being serviced (i1 and i0 in cc register). if an y of these two conditions is false, the interrupt is latched and thus remains pending. tli (top level hardware interrupt) caution: this hardware interrupt occurs when a specific edge is detected on the dedicated tli pin. it will be serviced according to the flowchart in figure 17 as a trap. a trap instruction must not be used in a tli service routine. external interrupts external interrupts allow the processor to exit from halt low power mode. external interrupt sensitivity is software selectable through the external interrupt control register (eicr). external interrupt trigger ed on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. if several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically ored. peripheral interrupts usually the peripheral interrupts cause the mcu to exit from halt mode except those mentioned in table 20: interrupt mapping . a peripheral interrupt occurs when a specific
interrupts st72321xx-auto 52/243 doc id 13829 rev 1 flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. the general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. note: the clearing sequence resets the internal latch. a pending interrupt (that is, waiting to be serviced) will therefore be lost if the clear sequence is executed. 7.3 interrupts and low power modes all interrupts allow the processor to exit the wait low power mode. on the contrary, only external and other specified interrupts allow the processor to exit from the halt modes (see column ?exit from halt/active halt? in table 20: interrupt mapping ). when several pending interrupts are present while exiting halt mode, the first one serviced can only be an interrupt with ?exit from halt mode? capa bility and it is selected thro ugh the same decision process shown in figure 18 . note: if an interrupt that is not able to exit from halt mode is pending with the highest priority when exiting halt mode, this interrupt is serviced after the first one serviced. 7.4 concurrent and nested management the following figure 19 and figure 20 show two different interrupt management modes. the first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in figure 20 . the interrupt hardware priority is given in this order from the lowest to the highest: main, it4, it3, it2, it1, it0, tli. the software priority is given for each interrupt. warning: a stack overflow may occur without notifying the software of the failure. figure 19. concurrent interrupt management main it4 it2 it1 trap it1 main it0 i1 hardware priority software 3 3 3 3 3 3/0 3 11 11 11 11 11 11 / 10 11 rim it2 it1 it4 trap it3 it0 it3 i0 10 priority level used stack = 10 bytes
st72321xx-auto interrupts doc id 13829 rev 1 53/243 figure 20. nested interrupt management 7.5 interrupt register description 7.5.1 cpu cc register interrupt bits these two bits indicate the current interrupt software priority (see ta b l e 1 7 ) and are set/cleared by hardware when entering in interrupt. the loaded value is given by the corresponding bits in the interrupt software priority registers (isprx). they can be also set/cleared by software with the rim, sim, halt, wfi, iret and push/pop instructions (see table 19: interrupt dedicated instruction set ). main it2 trap main it0 it2 it1 it4 trap it3 it0 hardware priority 3 2 1 3 3 3/0 3 11 00 01 11 11 11 rim it1 it4 it4 it1 it2 it3 i1 i0 11 / 10 10 software priority level used stack = 20 bytes cpu cc reset value: 111x 1010 (xah) 76543210 11 i1 h i0 nzc rw rw rw rw rw rw table 16. cpu cc register interrupt bits description bit name function 5i1 interrupt software priority 1 3i0 interrupt software priority 0
interrupts st72321xx-auto 54/243 doc id 13829 rev 1 7.5.2 interrupt software pr iority registers (isprx) these four registers are read/write, with the exception of bits 7:4 of ispr3, which are read only. these four registers contain the interrupt software priority of each interrupt vector. each interrupt vector (except reset and trap) has corresponding bits in these registers where its own software priority is stored. this correspondence is shown in the following ta b l e 1 8 . each i1_x and i0_x bit value in the isprx registers has the same meaning as the i1 and i0 bits in the cc register. level 0 cannot be written (i1_x = 1, i0_x = 0). in this case, the previously stored value is kept (example: previous = cfh, write = 64h, result = 44h). table 17. interrupt software priority levels interrupt software priority level i1 i0 level 0 (main) low high 10 level 1 0 1 level 2 0 0 level 3 (= interrupt disable (1) ) 1. tli, trap and reset events can interrupt a level 3 program. 11 isprx reset value: 1111 1111 (ffh) 76543210 ispr0 i1_3 i0_3 i1_2 i0_2 i1_1 i0_1 i1_0 i0_0 ispr1 i1_7 i0_7 i1_6 i0_6 i1_5 i0_5 i1_4 i0_4 ispr2 i1_11 i0_11 i1_10 i0_10 i1_9 i0_9 i1_8 i0_8 ispr3 1 1 1 1 i1_13 i0_13 i1_12 i0_12 table 18. interrupt priority bits vector address isprx bits fffbh-fffah i1_0 and i0_0 bits (1) 1. bits in the isprx registers which correspond to the tli can be read and written but they are not significant in the interrupt process management. fff9h-fff8h i1_1 and i0_1 bits ... ... ffe1h-ffe0h i1_13 and i0_13 bits
st72321xx-auto interrupts doc id 13829 rev 1 55/243 the tli, reset, and trap vectors have no so ftware priorities. when one is serviced, the i1 and i0 bits of the cc register are both set. caution: if the i1_x and i0_x bits are modified while the interrupt x is executed the following behavior has to be considered: if the inte rrupt x is still pending (new inte rrupt or flag not cleared) and the new software priority is higher than the previous one, the interrupt x is re-entered. otherwise, the software priority stays unchanged up to the next interrupt request (after the iret of the interrupt x). note: during the execution of an interrupt routine, the halt, popcc, rim, sim and wfi instructions change the current software priority up to the next iret instruction or one of the previously mentioned instructions. table 19. interrupt dedicated instruction set instruction new descriptio n function/example i1 h i0 n z c halt entering halt mode 1 0 iret interrupt routine return pop cc, a, x, pc i1 h i0 n z c jrm jump if i1:0 = 11 (level 3) i1:0 = 11 ? jrnm jump if i1:0 <> 11 i1:0 <> 11 ? pop cc pop cc from the stack mem => cc i1 h i0 n z c rim enable interrupt (level 0 set) load 10 in i1:0 of cc 1 0 sim disable interrupt (level 3 set) load 11 in i1:0 of cc 1 1 trap software trap software nmi 1 1 wfi wait for interrupt 1 0
interrupts st72321xx-auto 56/243 doc id 13829 rev 1 table 20. interrupt mapping no. source block description register label priority order exit from halt (1) address vector reset reset n/a yes fffeh-ffffh trap software interrupt no fffch-fffdh 0 tli external top level interrupt eicr yes fffah-fffbh 1 mcc/rtc main clock controller time base interrupt mccsr higher priority yes fff8h-fff9h 2 ei0 external interrupt port a3..0 n/a yes fff6h-fff7h 3 ei1 external interrupt port f2..0 yes fff4h-fff5h 4 ei2 external interrupt port b3..0 yes fff2h-fff3h 5 ei3 external interrupt port b7..4 yes fff0h-fff1h 6 not used ffeeh-ffefh 7 spi spi peripheral interrupts spicsr yes (2) ffech-ffedh 8 timer a timer a peripheral interrupts tasr no ffeah-ffebh 9 timer b timer b peripheral interrupts tbsr no ffe8h-ffe9h 10 sci sci peripheral interrupts scisr lower priority no ffe6h-ffe7h 11 avd auxiliary voltage detector interrupt sicsr no ffe4h-ffe5h 12 i2c i2c peripheral interrupts (see peripheral) no ffe2h-ffe3h 13 pwm art pwm art interrupt artcsr yes (3) ffe0h-ffe1h 1. in flash devices only a reset or mcc/rtc interru pt can be used to wake-up from active halt mode. 2. exit from halt possible when spi is in slave mode. 3. exit from halt possible when pw m art is in external clock mode.
st72321xx-auto interrupts doc id 13829 rev 1 57/243 7.6 external interrupts 7.6.1 i/o port in terrupt sensitivity the external interrupt sensitivity is controlled by the ipa, ipb and isxx bits of the eicr register ( figure 21 ). this control allows to have up to four fully independent external interrupt source sensitivities. each external interrupt source can be generated on four (or five) different events on the pin: falling edge rising edge falling and rising edge falling edge and low level rising edge and high level (only for ei0 and ei2) to guarantee correct functionality, the sensitivity bits in the eicr register can be modified only when the i1 and i0 bits of the cc register are both set to 1 (level 3). this means that interrupts must be disabled before changing sensitivity. the pending interrupts are cleared by writing a different value in the isx[1:0], ipa or ipb bits of the eicr.
interrupts st72321xx-auto 58/243 doc id 13829 rev 1 figure 21. external interrupt control bits is10 is11 eicr sensitivity control pbor.3 pbddr.3 ipb bit pb3 ei2 interrupt source port b [3:0] interrupts pb3 pb2 pb1 pb0 is10 is11 eicr sensitivity control pbor.7 pbddr.7 pb7 ei3 interrupt source port b [7:4] interrupts pb7 pb6 pb5 pb4 is20 is21 eicr sensitivity control paor.3 paddr.3 ipa bit pa3 ei0 interrupt source port a [3:0] interrupts pa3 pa2 pa1 pa0 is20 is21 eicr sensitivity control pfor.2 pfddr.2 pf2 ei1 interrupt source port f [2:0] interrupts pf2 pf1 pf0
st72321xx-auto interrupts doc id 13829 rev 1 59/243 7.6.2 external interrupt control register (eicr) eicr reset value: 0000 0000 (00h) 76543210 is1[1:0] ipb is2[1:0] ipa tlis tlie rw rw rw rw rw rw table 21. eicr register description bit name function 7:6 is1[1:0] ei2 and ei3 sensitivity the interrupt sensitivity, defined using the is1[1:0] bits, is applied to the following external interrupts: - ei2 (port b3..0) (see ta bl e 2 2 ) - ei3 (port b7..4) (see ta bl e 2 3 ) these 2 bits can be written only when i1 and i0 of the cc register are both set to 1 (level 3). 5ipb interrupt polarity for port b this bit is used to invert the sensitivity of the port b [3:0] external interrupts. it can be set and cleared by software only when i1 and i0 of the cc register are both set to 1 (level 3). 0: no sensitivity inversion 1: sensitivity inversion 4:3 is2[1:0] ei0 and ei1 sensitivity the interrupt sensitivity, defined using the is2[1:0] bits, is applied to the following external interrupts: - ei0 (port a3..0) (see ta bl e 2 4 ) - ei1 (port f2..0) (see ta b l e 2 5 ) these 2 bits can be written only when i1 and i0 of the cc register are both set to 1 (level 3). 2ipa interrupt polarity for port a this bit is used to invert the sensitivity of the port a [3:0] external interrupts. it can be set and cleared by software only when i1 and i0 of the cc register are both set to 1 (level 3). 0: no sensitivity inversion 1: sensitivity inversion 1tlis tli sensitivity this bit allows to toggle the tli edge sensitivity. it can be set and cleared by software only when tlie bit is cleared. 0: falling edge 1: rising edge 0tlie tli enable this bit allows to enable or disable the tli capability on the dedicated pin. it is set and cleared by software. 0: tli disabled 1: tli enabled note: a parasitic interrupt can be generated when clearing the tlie bit.
interrupts st72321xx-auto 60/243 doc id 13829 rev 1 table 22. interrupt sensitivity - ei2 (port b3..0) is11 is10 external interr upt sensitivity ipb bit = 0 ipb bit = 1 0 0 falling edge and low level rising edge and high level 0 1 rising edge only falling edge only 1 0 falling edge only rising edge only 1 1 rising and falling edge table 23. interrupt sensitivity - ei3 (port b7..4) is11 is10 external interrupt sensitivity 0 0 falling edge and low level 0 1 rising edge only 1 0 falling edge only 1 1 rising and falling edge table 24. interrupt sensitivity - ei0 (port a3..0) is21 is20 external interr upt sensitivity ipa bit = 0 ipa bit = 1 0 0 falling edge and low level rising edge and high level 0 1 rising edge only falling edge only 1 0 falling edge only rising edge only 1 1 rising and falling edge table 25. interrupt sensitivity - ei1 (port f2..0) is21 is20 external interrupt sensitivity 0 0 falling edge and low level 0 1 rising edge only 1 0 falling edge only 1 1 rising and falling edge
st72321xx-auto interrupts doc id 13829 rev 1 61/243 table 26. nested interrupts register map and reset values address (hex.)register label76543210 0024h ispr0 reset value ei1 ei0 mcc tli i1_3 1 i0_3 1 i1_2 1 i0_2 1 i1_1 1 i0_1 111 0025h ispr1 reset value spi reserved ei3 ei2 i1_7 1 i0_7 1 i1_6 1 i0_6 1 i1_5 1 i0_5 1 i1_4 1 i0_4 1 0026h ispr2 reset value avd sci timer b timer a i1_11 1 i0_11 1 i1_10 1 i0_10 1 i1_9 1 i0_9 1 i1_8 1 i0_8 1 0027h ispr3 reset value 1 1 1 1 pwmart i2c i1_13 1 i0_13 1 i1_12 1 i0_12 1 0028h eicr reset value is11 0 is10 0 ipb 0 is21 0 is20 0 ipa 0 tlis 0 tlie 0
power saving modes st72321xx-auto 62/243 doc id 13829 rev 1 8 power saving modes 8.1 introduction to give a large measure of flexibility to the ap plication in terms of power consumption, four main power saving modes are implemented in the st7 (see figure 22 ): slow, wait (slow wait), active halt and halt. after a reset the normal operat ing mode is selected by defa ult (run mode). this mode drives the device (cpu and embedded periphera ls) by means of a master clock which is based on the main osc illator frequency divided or multiplied by 2 (f osc2 ). from run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific st7 software instructi on whose action depends on the oscillator status. figure 22. power saving mode transitions 8.2 slow mode this mode has two targets: to reduce power consumption by decreasing the internal clock in the device, to adapt the internal clock frequency (f cpu ) to the available supply voltage. slow mode is controlled by three bits in the mccsr register: the sms bit which enables or disables slow mode and two cpx bits which select the internal slow frequency (f cpu ). in this mode, the master clock frequency (f osc2 ) can be divided by 2, 4, 8 or 16. the cpu and peripherals are clocked at this lower frequency (f cpu ). note: slow wait mode is activate d when entering the wait mode while the device is already in slow mode. power consumption wait slow run active halt high low slow wait halt
st72321xx-auto power saving modes doc id 13829 rev 1 63/243 figure 23. slow mode clock transitions 8.3 wait mode wait mode places the mcu in a low power consumption mode by stopping the cpu. this power saving mode is selected by calling the ?wfi? instruction. all peripherals remain active. during wait mode, the i[1:0] bits of the cc register are forced to ?10?, to enable all interrupts. all other registers and memory remain unchanged. the mcu remains in wait mode until an interrupt or reset occurs, whereupon the program counter branches to the starting address of the interrupt or reset service routine. the mcu will remain in wait mode until a reset or an interrupt occurs, causing it to wake up. refer to the following figure 24 . 00 01 sms cp1:0 f cpu new slow normal run mode mccsr frequency request request f osc2 f osc2/2 f osc2/4 f osc2
power saving modes st72321xx-auto 64/243 doc id 13829 rev 1 figure 24. wait mode flowchart 1. before servicing an interrupt, the cc register is pushed on the stack. the i[1:0] bits of the cc register are set to the current software priority level of the inte rrupt routine and recovered when the cc register is popped. wfi instruction reset interrupt y n n y cpu oscillator peripherals i[1:0] bits on on 10 off fetch reset vector or service interrupt cpu oscillator peripherals i[1:0] bits on off 10 on cpu oscillator peripherals i[1:0] bits on on xx (1) on 256 or 4096 cpu clock cycle delay
st72321xx-auto power saving modes doc id 13829 rev 1 65/243 8.4 active halt and halt modes active halt and halt modes are the two lowest power consumption modes of the mcu. they are both entered by executing the ?halt? instruction. the decision to enter either in active halt or halt mode is given by the mcc/rt c interrupt enable flag (oie bit in mccsr register) as shown in ta bl e 2 7 . 8.4.1 active halt mode active halt mode is the lowest power consumption mode of the mcu with a real-time clock available. it is entered by executing the ?halt? instruction when the oie bit of the main clock controller status register (mccsr) is set (see section 12.3: art registers on page 93 for more details on the mccsr register). the mcu can exit active halt mode on re ception of an mcc/rtc interrupt or a reset. when exiting active halt mode by means of an interrupt, no 256 or 4096 cpu cycle delay occurs. the cpu resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see figure 26 ). when entering active halt mode, the i[1:0] bits in the cc register are forced to ?10b? to enable interrupts. therefore, if an interrup t is pending, the mcu wakes up immediately. in active halt mode, only the main oscilla tor and its associated counter (mcc/rtc) are running to keep a wake-up time base. all ot her peripherals are not clocked except those which get their clock supply from another cloc k generator (such as external or auxiliary oscillator). the safeguard against staying locked in active halt mode is provided by the oscillator interrupt. note: as soon as the interrupt capab ility of one of the oscillators is selected (mccsr.oie bit set), entering active halt mode while the watchdog is active does not generate a reset. this means that the device cannot spend more than a defined delay in this power saving mode. caution: when exiting active halt mode following an mc c/rtc interrupt, oie bit of mccsr register must not be cleared before t delay after the interrupt occurs (t delay = 256 or 4096 t cpu delay depending on option byte). otherwise, the st7 enters halt mode for the remaining t delay period. table 27. mcc/rtc low power mode selection mccsr oie bit power saving mode entered when halt instruction is executed 0halt 1 active halt
power saving modes st72321xx-auto 66/243 doc id 13829 rev 1 figure 25. active halt timing overview 1. this delay occurs only if the mcu exits active halt mode by means of a reset. figure 26. active halt mode flowchart 1. peripheral clocked with an external clock source can still be active. 2. before servicing an interrupt, the cc register is pushed on the stack. the i[1:0] bits of the cc register are set to the current software priority level of the inte rrupt routine and restored when the cc register is popped. 3. in flash devices only the m cc/rtc interrupt can exit the mcu from active halt mode. halt run run 256 or 4096 cpu cycle delay (1) reset or interrupt halt instruction fetch vector active [mccsr.oie = 1] halt instruction reset y n n y cpu oscillator peripherals (1) i[1:0] bits on off 10 off fetch reset vector or service interrupt cpu oscillator peripherals i[1:0] bits on off xx (2) on cpu oscillator peripherals i[1:0] bits on on xx (2) on 256 or 4096 cpu clock cycle delay (mccsr.oie = 1) interrupt (3)
st72321xx-auto power saving modes doc id 13829 rev 1 67/243 8.4.2 halt mode the halt mode is the lowest power consumption mode of the mcu. it is entered by executing the ?halt? instruction when the oie bit of the main clock controller status register (mccsr) is cleared (see section 11: main clock controller with real-time clock and beeper (mcc/rtc) on page 82 for more details on the mccsr register). the mcu can exit halt mode on reception of either a specific interrupt (see section table 20.: interrupt mapping on page 56 ) or a reset. when exiting halt mode by means of a reset or an interrupt, the os cillator is immediately turned on and the 256 or 4096 cpu cycle delay is used to stabilize the oscillator. after the start up de lay, the cpu resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see figure 28 ). when entering halt mode, the i[1:0] bits in the cc register are forced to ?10b? to enable interrupts. therefore, if an interrupt is pending, the mcu wakes up immediately. in halt mode, the main oscillator is turned off causing all intern al processing to be stopped, including the operation of the on-chip peripherals. all peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator). the compatibility of watc hdog operation with halt mode is configured by the ?wdghalt? option bit of the option byte. the halt instruction when executed while the watchdog system is enabled, can gener ate a watchdog reset (see section 21.1.1: flash configuration on page 223 for more details). figure 27. halt timing overview halt run run 256 or 4096 cpu cycle delay reset or interrupt halt instruction fetch vector [mccsr.oie = 0]
power saving modes st72321xx-auto 68/243 doc id 13829 rev 1 figure 28. halt mode flowchart 1. wdghalt is an option bit. see section 21.1.1: flash configuration on page 223 for more details. 2. peripheral clocked with an external clock source can still be active. 3. only some specific interrupts can exit the mcu from halt mode (such as external interrupt). refer to table 20: interrupt mapping for more details. 4. before servicing an interrupt, the cc register is pushed on the stack. the i[1:0] bits of the cc register are set to the current software priority level of the inte rrupt routine and recovered when the cc register is popped. halt instruction reset interrupt (3) y n n y cpu oscillator peripherals (2) i[1:0] bits off off 10 off fetch reset vector or service interrupt cpu oscillator peripherals i[1:0] bits on off xx (4) on cpu oscillator peripherals i[1:0] bits on on xx (4) on 256 or 4096 cpu clock delay watchdog enable disable wdghalt (1) 0 watchdog reset 1 (mccsr.oie = 0) cycle
st72321xx-auto power saving modes doc id 13829 rev 1 69/243 halt mode recommendations make sure that an external event is available to wake up the microcontroller from halt mode. when using an external interrupt to wake up the microcontroller, re-initialize the corresponding i/o as ?input pull-up with interrupt? before executing the halt instruction. the main reason for this is that the i/o may be wrongly configured due to external interference or by an unforeseen logical condition. for the same reason, reinitialize the level sens itiveness of each external interrupt as a precautionary measure. the opcode for the halt instruction is 0x8e . to avoid an unexpected halt instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8e from memory. for example, avoid defining a constant in rom with the value 0x8e. as the halt instruction clears the interrupt ma sk in the cc register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the halt instruction. this avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt). related documentation st7 keypad decoding techniques, implementing wake-up on keystroke (an 980) how to minimize the st7 power consumption (an1014) using an active rc to wake up the st7lite0 from power saving mode (an1605)
i/o ports st72321xx-auto 70/243 doc id 13829 rev 1 9 i/o ports 9.1 introduction the i/o ports offer different functional modes: transfer of data through digital inputs and outputs and for specific pins: external interrupt generation alternate signal input/output for the on-chip peripherals. an i/o port contains up to eight pins. each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 9.2 functional description each port has two main registers: data register (dr) data direction register (ddr) and one optional register: option register (or) each i/o pin may be programmed using the corresponding register bits in the ddr and or registers (bit x corresponding to pin x of the port). the same correspondence is used for the dr register. the following description takes into account the or register (for specific ports which do not provide this register refer to section 9.3: i/o port implementation on page 74 ). the generic i/o block diagram is shown in figure 29 . 9.2.1 input modes the input configuration is selected by clearing the corresponding ddr register bit. in this case, reading the dr register returns the digital value applied to the external i/o pin. different input modes can be selected by software through the or register. note: 1 writing the dr register modifies the latch value but does not affect the pin status. 2 when switching from input to output mode, the dr register has to be written first to drive the correct level on the pin as soon as the port is configured as an output. 3 do not use read/modify/write instructions (bset or bres) to modify the dr register as this might corrupt the dr content for i/os configured as input. external interrupt function when an i/o is configured as input with interrupt, an event on this i/o can generate an external interrupt request to the cpu. each pin can independently generate an interrupt request. the interrupt sensitivity is independently programmable using the sensitivity bits in the eicr register.
st72321xx-auto i/o ports doc id 13829 rev 1 71/243 each external interrupt vector is linked to a dedicated group of i/o port pins (see pinout description and interrupt section). if several input pins are selected simultaneously as interrupt sources, these are first detected according to the sensitivity bits in the eicr register and then logically ored. the external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. to clear an unwanted pending interrupt by software, the sensitivity bits in the eicr register must be modified. 9.2.2 output modes the output conf iguration is selected by setting the co rresponding ddr regist er bit. in this case, writing the dr register applies this digital value to the i/o pin through the latch. then reading the dr register returns the previously stored value. two different output modes can be selected by software through the or register: output push-pull and open-drain. the dr register value and output pin status are shown in the following ta b l e 2 8 . 9.2.3 alternate functions when an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. this alternate function takes priority over the standard i/o programming. when the signal is coming from an on-chip peripheral, the i/o pin is automatically configured in output mode (push-pull or open-drain according to the peripheral). when the signal is going to an on-chip peripheral, the i/o pin must be configured in input mode. in this case, the pin state is also digi tally readable by addressing the dr register. note: input pull-up configuration can cause unexpected value at the input of the alternate peripheral input. when an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode. table 28. i/o output mode selection dr push-pull open-drain 0v ss v ss 1v dd floating
i/o ports st72321xx-auto 72/243 doc id 13829 rev 1 figure 29. i/o port general block diagram table 29. i/o port mode options configuration mode pull-up p-buffer diodes to v dd to v ss input floating with/without interrupt off off on on pull-up with/without interrupt on output push-pull off on open-drain (logic level) off true open-drain ni ni ni (1) 1. the diode to v dd is not implemented in the true open-drain pads. a local protection between the pad and v ss is implemented to protect the device against positive stress. legend: off - implemented not activated on - implemented and activated ni - not implemented dr ddr or data bus pad v dd alternate enable alternate output 1 0 or sel ddr sel dr sel pull-up condition p-buffer (see table below) n-buffer pull-up (see table below) 1 0 analog input if implemented alternate input v dd diodes (see table below) external source (ei x ) interrupt cmos schmitt trigger register access
st72321xx-auto i/o ports doc id 13829 rev 1 73/243 table 30. i/o port configurations hardware configuration input (1) open-drain output (2) push-pull output (2) 1. when the i/o port is in input configuration and the associat ed alternate function is enabled as an output, reading the dr register will read the alternate function output status. 2. when the i/o port is in output configuration and the asso ciated alternate function is enabl ed as an input, the alternate function reads the pin status given by the dr register content. condition pa d v dd r pu external interrupt data bus pull-up interrupt dr register access w r source (ei x ) dr register condition alternate input not implemented in true open drain i/o ports analog input pa d r pu data bus dr dr register access r/w v dd alternate alternate enable output register not implemented in true open drain i/o ports pa d r pu data bus dr dr register access r/w v dd alternate alternate enable output register not implemented in true open drain i/o ports
i/o ports st72321xx-auto 74/243 doc id 13829 rev 1 caution: the alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. analog alternate function when the pin is used as an adc input, the i/o must be configured as floating input. the analog multiplexer (controlled by the adc registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the adc input. it is recommended not to change the voltage level or loading on any port pin while conversion is in progress. furthermore it is recommended not to have clocking pins located close to a selected analog pin. warning: the analog input voltage level must be within the limits stated in the absolute maximum ratings. 9.3 i/o port implementation the hardware implementation on each i/o port depends on the settings in the ddr and or registers and specific feature of the i/o port such as adc input or true open-drain. switching these i/o ports from one state to another should be done in a sequence that prevents unwanted side effects. recommend ed safe transitions are illustrated in figure 30 . other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. figure 30. interrupt i/o port state transitions the i/o port register configurations are summarized in the following table. table 31. i/o port configuration port pin name input (ddr = 0) output (ddr = 1) or = 0 or = 1 or = 0 or = 1 port a pa7:6 floating true open-drain pa5:4 floating pull-up open-drain push-pull pa3 floating floating interrupt open-drain push-pull pa2:0 floating pull-up interrupt open-drain push-pull 01 floating/pull-up interrupt input 00 floating (reset state) input 10 open-drain output 11 push-pull output xx = ddr, or
st72321xx-auto i/o ports doc id 13829 rev 1 75/243 9.4 low power modes 9.5 interrupts the external interrupt event generates an interrupt if the corresponding configuration is selected with ddr and or registers and the interrupt mask in the cc register is not active (rim instruction). port b pb7, pb3 floating floating interrupt open-drain push-pull pb6:5, pb4, pb2:0 floating pull-up interrupt open-drain push-pull port c pc7:0 floating pull-up open-drain push-pull port d pd7:0 floating pull-up open-drain push-pull port e pe7:3, pe1:0 floating pull-up open drain push-pull pe2 (flash devices) pull-up input only pe2 (rom devices) floating open drain push-pull port f pf7:3 floating pull-up open-drain push-pull pf2 floating floating interrupt open-drain push-pull pf1:0 floating pull-up interrupt open-drain push-pull table 31. i/o port configuration (continued) port pin name input (ddr = 0) output (ddr = 1) or = 0 or = 1 or = 0 or = 1 table 32. effect of low power modes on i/o ports mode effect wait no effect on i/o ports. external interrupt s cause the device to exit from wait mode. halt no effect on i/o ports. external interrupt s cause the device to exit from halt mode. table 33. i/o port interrupt control/wake-up capability interrupt event event flag enable control bit exit from wait exit from halt external interrupt on selected external event - ddrx, orx yes yes table 34. i/o port register map and reset values address (hex.)register label76543210 reset value of all i/o port registers00000000 0000h padr msb lsb 0001h paddr 0002h paor
i/o ports st72321xx-auto 76/243 doc id 13829 rev 1 related documentation spi communication bet ween st7 and eeprom (an 970) s/w implementation of i2c bus maste r (an1045) software lcd driver (an1048) 0003h pbdr msb lsb 0004h pbddr 0005h pbor 0006h pcdr msb lsb 0007h pcddr 0008h pcor 0009h pddr msb lsb 000ah pdddr 000bh pdor 000ch pedr msb lsb 000dh peddr 000eh peor 000fh pfdr msb lsb 0010h pfddr 0011h pfor table 34. i/o port register map and reset values (continued) address (hex.)register label76543210 reset value of all i/o port registers00000000
st72321xx-auto watchdog timer (wdg) doc id 13829 rev 1 77/243 10 watchdog timer (wdg) 10.1 introduction the watchdog timer is used to detect the oc currence of a software fault, usually generated by external interference or by unforeseen lo gical conditions, which causes the application program to abandon its normal sequence. the watchdog circuit generates an mcu reset on expiry of a programmed time period, unless the program refreshes the counter?s contents before the t6 bit becomes cleared. 10.2 main features programmable free-running downcounter programmable reset reset (if watchdog activated) when the t6 bit reaches zero optional reset on halt instruction (configurable by option byte) hardware watchdog selectable by option byte 10.3 functional description the counter value stored in the watchdog control register (wdgcr bits t[6:0]), is decremented every 16384 f osc2 cycles (approx.), and the lengt h of the timeout period can be programmed by the user in 64 increments. if the watchdog is activated (the wdga bit is set) and when the 7-bit timer (bits t[6:0]) rolls over from 40h to 3fh (t6 becomes cleared) , it initiates a rese t cycle pulling the reset pin low for typically 30s. the application program must write in the wd gcr register at regular intervals during normal operation to prevent an mcu reset. this downcounter is free-running: it counts down even if the watchdog is disabled. the value to be stored in the wdgcr register must be between ffh and c0h: ? the wdga bit is set (watchdog enabled) ? the t6 bit is set to prevent generating an immediate reset ? the t[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset (see figure 32: approximate timeout duration ). the timing varies between a minimum and a maximum value due to the unknown status of the prescaler when writing to the wdgcr register (see figure 33 ). following a reset, the watchdog is disabled. once activated it cannot be disabled, except by a reset. the t6 bit can be used to generate a software re set (the wdga bit is set and the t6 bit is cleared). if the watchdog is activated, the halt instruction will generate a reset.
watchdog timer (wdg) st72321xx-auto 78/243 doc id 13829 rev 1 figure 31. watchdog block diagram 10.4 how to program the watchdog timeout figure 32 shows the linear relationship between the 6-bit value to be loaded in the watchdog counter (cnt) and th e resulting timeout duration in milliseconds. this can be used for a quick calculation without taking the timing variations into account. if more precision is needed, use the formulae in figure 33 . caution: when writing to the wdgcr register, always write 1 in the t6 bit to avoid generating an immediate reset. figure 32. approximate timeout duration reset wdga 6-bit downcounter (cnt) f osc2 t6 t0 wdg prescaler watchdog control register (wdgcr) div 4 t1 t2 t3 t4 t5 12-bit mcc rtc counter msb lsb div 64 0 6 11 mcc/rtc tb[1:0] bits (mccsr register) 5 cnt value (hex.) watchdog timeout (ms) @ 8 mhz f osc2 3f 00 38 128 1.5 65 30 28 20 18 10 08 50 34 18 82 98 114
st72321xx-auto watchdog timer (wdg) doc id 13829 rev 1 79/243 figure 33. exact timeout duration (t min and t max ) where : t min0 = (lsb + 128) x 64 x t osc2 t max0 = 16384 x t osc2 t osc2 = 125ns if f osc2 =8 mhz cnt = value of t[5:0] bits in the wdgcr register (6 bits) msb and lsb are values from the table below de pending on the timebase selected by the tb[1:0] bits in the mccsr register to calculate the minimum watchdog timeout (t min ): if then else to calculate the maximum watchdog timeout (t max ): if then else note: in the above formulae, division results must be rounded down to the next integer value. example: with 2ms timeout selected in mccsr register tb1 bit (mccsr reg.) tb0 bit (mccsr reg.) selected mccsr timebase msb lsb 0 0 2ms 4 59 0 1 4ms 8 53 1 0 10ms 20 35 1 1 25ms 49 54 value of t[5:0] bits in wdgcr register (hex.) min. watchdog timeout (ms) t min max. watchdog timeout (ms) t max 00 1.496 2.048 3f 128 128.552 cnt msb 4 ------------- < t min t min0 16384 cnt t osc2 ? ? + = t min t min0 16384 cnt 4cnt msb ---------------- - ? ?? ?? ? 192 lsb + ?? 64 4cnt msb ---------------- - ? ? + t osc2 ? + = cnt msb 4 ------------- ? t max t max0 16384 cnt t osc2 ? ? + = t max t max0 16384 cnt 4cnt msb ---------------- - ? ?? ?? ? 192 lsb + ?? 64 4cnt msb ---------------- - ? ? + t osc2 ? + =
watchdog timer (wdg) st72321xx-auto 80/243 doc id 13829 rev 1 10.5 low power modes 10.6 hardware watchdog option if hardware watchdog is selected by option byte, the watchdog is always active and the wdga bit in the wdgcr is not used. refer to the option byte description in section 21.1.1: flash configuration on page 223 . 10.7 using halt mode with the wdg (wdghalt option) the following recommendation applies if halt mode is used when the watchdog is enabled: before executing the halt instruction, refresh the wdg counter to avoid an unexpected wdg reset immediately after waking up the microcontroller. 10.8 interrupts none. table 35. effect of low power modes on wdg mode effect slow no effect on watchdog wait no effect on watchdog halt oie bit in mccsr register wdghalt bit in option byte 00 no watchdog reset is generated. the mcu enters halt mode. the watchdog counter is decrem ented once and then stops counting and is no longer able to generate a watchdog reset until the mcu receives an external interrupt or a reset. if an external interrupt is received, the watchdog restarts counting after 256 or 4096 cpu clocks. if a reset is generated, the watchdog is disabled (reset state) unless hardware watchdog is selected by option byte. for application recommendations see section 10.7 below. 0 1 a reset is generated. 1x no reset is generated. the mcu enters active halt mode. the watchdog counter is not decreme nted. it stop counting. when the mcu receives an oscillator interrupt or external interrupt, the watchdog restarts counting immediately. when the mcu receives a reset the watchdog restarts counting after 256 or 4096 cpu clocks.
st72321xx-auto watchdog timer (wdg) doc id 13829 rev 1 81/243 10.9 register description 10.9.1 control register (wdgcr) wdgcr reset value: 0111 1111 (7fh) 76543210 wdga t[6:0] rw rw table 36. wdgcr register description bit name function 7wdga activation bit this bit is set by software and only cleared by hardware after a reset. when wdga = 1, the watchdog can generate a reset. 0: watchdog disabled 1: watchdog enabled note: this bit is not used if the hardware watchdog option is enabled by option byte. 6:0 t[6:0] 7-bit counter (msb to lsb) these bits contain the value of the watc hdog counter. it is decremented every 16384 f osc2 cycles (approx.). a reset is produced when it rolls over from 40h to 3fh (t6 becomes cleared). table 37. watchdog timer register map and reset values address (hex.) register label 76543210 002ah wdgcr reset value wdga 0 t6 1 t5 1 t4 1 t3 1 t2 1 t1 1 t0 1
main clock controller with real-time clock and beeper (mcc/rtc) st72321xx-auto 82/243 doc id 13829 rev 1 11 main clock controller with real-time clock and beeper (mcc/rtc) 11.1 introduction the main clock controller consists of three different functions: a programmable cpu clock prescaler a clock-out signal to supply external devices a real-time clock timer with interrupt capability each function can be used independently and simultaneously. 11.2 programmable cpu clock prescaler the programmable cpu clock prescaler supplies the clock for the st7 cpu and its internal peripherals. it manages slow power saving mode (see section 8.2: slow mode on page 62 for more details). the prescaler selects the f cpu main clock frequency and is controlled by three bits in the mccsr register: cp[1:0] and sms. 11.3 clock-out capability the clock-out capability is an alternate functi on of an i/o port pin that outputs a f cpu clock to drive external devices. it is controlled by the mco bit in the mccsr register. caution: when selected, the clock out pin suspends the clock during active halt mode. 11.4 real-time clock timer (rtc) the counter of the real-time clock timer allows an interrupt to be generated based on an accurate real-time clock. four different time bases depending directly on f osc2 are available. the whole functionality is controlled by four bits of the mccsr register: tb[1:0], oie and oif. when the rtc interrupt is enabled (oie bit set), the st7 enters active halt mode when the halt instruction is executed. see section 8.4: active halt and halt modes on page 65 for more details. 11.5 beeper the beep function is controlled by the mccbcr register. it can output three selectable frequencies on the beep pin (i/o port alternate function).
st72321xx-auto main clock controller with real-time clock and beeper (mcc/rtc) doc id 13829 rev 1 83/243 figure 34. main clock controller (mcc/rtc) block diagram 11.6 low power modes 11.7 interrupts the mcc/rtc interrupt event generates an interrupt if the oie bit of the mccsr register is set and the interrupt mask in the cc register is not active (rim instruction). div 2, 4, 8, 16 mcc/rtc interrupt sms cp1 cp0 tb1 tb0 oie oif cpu clock mccsr 12-bit mcc rtc counter to cpu and peripherals f osc2 f cpu mco mco bc1 bc0 mccbcr beep selection beep signal 1 0 to watchdog timer div 64 table 38. effect of low power modes on mcc/rtc mode effect wait no effect on mcc/rtc peripheral. mcc/rtc interrupt causes the devi ce to exit from wait mode. active halt no effect on mcc/rtc counter (oie bit is set), the registers are frozen. mcc/rtc interrupt causes the device to exit from active halt mode. halt mcc/rtc counter and registers are frozen. mcc/rtc operation resumes when the mcu is woken up by an interrupt with ?exit from halt? capability. table 39. mcc/rtc interrupt control/wake-up capability interrupt event event flag enable control bit exit from wait exit from halt time base overflow event oif oie yes no (1) 1. the mcc/rtc interrupt wakes up the mcu from active halt mode, not from halt mode.
main clock controller with real-time clock and beeper (mcc/rtc) st72321xx-auto 84/243 doc id 13829 rev 1 11.8 main clock controller registers 11.8.1 mcc control/status register (mccsr) mccsr reset value: 0000 0000 (00h) 76543210 mco cp[1:0] sms tb[1:0] oie oif rw rw rw rw rw rw table 40. mccsr register description bit name function 7mco main clock out selection this bit enables the mco alternate function on the pf0 i/o port. it is set and cleared by software. 0: mco alternate function disabled (i/o pin free for general-purpose i/o) 1: mco alternate function enabled (f cpu on i/o port) note: to reduce power consumption, the mco function is not active in active halt mode. 6:5 cp[1:0] cpu clock prescaler these bits select the cpu clock prescaler which is applied in the different slow modes. their action is conditioned by the setting of the sms bit. these two bits are set and cleared by software. 00: f cpu in slow mode = f osc2 /2 01: f cpu in slow mode = f osc2 /4 10: f cpu in slow mode = f osc2 /8 11: f cpu in slow mode = f osc2 /16 4sms slow mode select this bit is set and cleared by software. 0: normal mode. f cpu = f osc2 1: slow mode. f cpu is given by cp1, cp0 see section 8.2: slow mode on page 62 and chapter 11: main clock controller with real-time clock and beeper (mcc/rtc) for more details. 3:2 tb[1:0] time base control these bits select the programmable divider time base. they are set and cleared by software (see ta b l e 4 1 ) . a modification of the time base is taken in to account at the end of the current period (previously set) to avoid an unwanted time sh ift. this allows to use this time base as a real-time clock. 1oie oscillator interrupt enable this bit set and cleared by software. 0: oscillator interrupt disabled 1: oscillator interrupt enabled this interrupt can be used to exit from active halt mode. when this bit is set, calling the st7 softwa re halt instruction enters the active halt power saving mode .
st72321xx-auto main clock controller with real-time clock and beeper (mcc/rtc) doc id 13829 rev 1 85/243 11.8.2 mcc beep control register (mccbcr) the beep output signal is available in active halt mode but has to be disabled to reduce consumption. 0oif oscillator interrupt flag this bit is set by hardware and cleared by software reading the mccsr register. it indicates when set that the main oscillator has reached the selected elapsed time (tb1:0). 0: timeout not reached 1: timeout reached caution : the bres and bset instructions must not be used on the mccsr register to avoid unintentionally clearing the oif bit. table 41. time base selection counter prescaler time base tb1 tb0 f osc2 =4mhz f osc2 =8mhz 16000 4ms 2ms 0 0 32000 8ms 4ms 0 1 80000 20ms 10ms 1 0 200000 50ms 25ms 1 1 table 40. mccsr register description (continued) bit name function mccbcr reset value: 0000 0000 (00h) 76543210 reserved bc[1:0] -rw table 42. mccbcr register description bit name function 7:2 - reserved, must be kept cleared. 1:0 bc[1:0] beep control these 2 bits select the pf1 pin beep capability (see ta bl e 4 3 ). table 43. beep frequency selection bc1 bc0 beep mode with f osc2 =8mhz 00 off 0 1 ~2 khz output beep signal ~50% duty cycle 1 0 ~1 khz 11 ~500hz
main clock controller with real-time clock and beeper (mcc/rtc) st72321xx-auto 86/243 doc id 13829 rev 1 table 44. main clock controller register map and reset values address (hex.) register label 76543210 002bh sicsr reset value avds 0 avdie 0 avdf 0 lv d r f x000 wdgrf x 002ch mccsr reset value mco 0 cp1 0 cp0 0 sms 0 tb1 0 tb0 0 oie 0 oif 0 002dh mccbcr reset value000000 bc1 0 bc0 0
st72321xx-auto pwm auto-reload timer (art) doc id 13829 rev 1 87/243 12 pwm auto-reload timer (art) 12.1 introduction the pulse width modulated auto-reload timer on-chip peripheral consists of an 8-bit auto- reload counter with compare/ca pture capabilities and of a 7- bit prescaler clock source. these resources allow five possible operating modes: generation of up to 4 independent pwm signals output compare and time base interrupt up to 2 input capture functions external event detector up to 2 external interrupt sources the three first modes can be used together with a single counter frequency. the timer can be used to wake up the mcu from wait and halt modes. figure 35. pwm auto-reload timer block diagram ovf interrupt excl cc2 cc1 cc0 tce fcrl oie ovf artcsr f input pwmx port function alternate ocrx compare register programmable prescaler arr register icrx register load opx polarity control oex pwmcr mux f cpu dcrx register load f counter artclk f ext articx icfx icsx iccsr load icx interrupt iciex input capture control 8-bit counter (car register)
pwm auto-reload timer (art) st72321xx-auto 88/243 doc id 13829 rev 1 12.2 functional description 12.2.1 counter the free running 8-bit counter is fed by the output of the prescaler, and is incremented on every rising edge of the clock signal. it is possible to read or write the contents of the counter on the fly by reading or writing the counter access register (artcar). when a counter overflow occurs, the counter is automatically reloaded with the contents of the artarr register (the prescaler is not affected). 12.2.2 counter clock and prescaler the counter clock frequency is given by: f counter = f input / 2 cc[2:0] the timer counter?s input clock (f input ) feeds the 7-bit programmable prescaler, which selects one of the 8 available taps of the prescaler, as defined by cc[2:0] bits in the control/status register (artcsr). thus the division factor of the prescaler can be set to 2 n (where n = 0, 1,..7). this f input frequency source is selected through the excl bit of the artcsr register and can be either the f cpu or an external input frequency f ext . the clock input to the counter is enabled by the tce (timer counter enable) bit in the artcsr register. when tce is reset, the counter is stopped and the prescaler and counter contents are frozen. when tce is set, the counter runs at the rate of the selected clock source. 12.2.3 counter and pre scaler initialization after reset, the counter and th e prescaler are cleared and f input = f cpu . the counter can be initialized by: writing to the artarr register and then setting the fcrl (force counter re-load) and the tce (timer counter enable) bits in the artcsr register writing to the artcar counter access register in both cases the 7-bit presca ler is also cleared, whereupon counting will start from a known value. direct access to the pre scaler is not possible. 12.2.4 output compare control the timer compare function is based on four different comparisons with the counter (one for each pwmx output). each comparison is made between the counter value and an output compare register (ocrx) value. this ocrx regi ster can not be accessed directly, it is loaded from the duty cycle register (pwmdcrx) at each overflow of the counter. this double buffering method avoids glitch generation when changing the duty cycle on the fly.
st72321xx-auto pwm auto-reload timer (art) doc id 13829 rev 1 89/243 figure 36. output compare control 12.2.5 independent pwm signal generation this mode allows up to four pulse width modulated signals to be generated on the pwmx output pins with minimum core processing overhead. this function is stopped during halt mode. each pwmx output signal can be selected i ndependently using the corresponding oex bit in the pwm control register (pwmcr). when this bit is set, the corresponding i/o pin is configured as output push-pull alternate function. the pwm signals all have the same frequency which is controlled by the counter period and the artarr register value. f pwm = f counter / (256 - artarr) when a counter overflow occurs, the pwmx pin level is changed depending on the corresponding opx (output polarity) bit in the pwmcr register. when the counter reaches the value contained in one of the output compare register (ocrx) the corresponding pwmx pin level is restored. it should be noted that the reload values will also affect the value and the resolution of the duty cycle of the pwm output signal. to obtain a signal on a pwmx pin, the contents of the ocrx register must be greater than the contents of the artarr register. the maximum available resolution for the pwmx duty cycle is: resolution = 1 / (256 - artarr) note: to get the maximum resolution (1/256), the artarr register must be 0. with this maximum resolution, 0% and 100% can be obtained by changing the polarity. counter fdh feh ffh fdh feh ffh fdh feh artarr = fdh f counter ocrx pwmdcrx fdh feh fdh feh ffh pwmx
pwm auto-reload timer (art) st72321xx-auto 90/243 doc id 13829 rev 1 figure 37. pwm auto-reload timer function figure 38. pwm signal from 0% to 100% duty cycle 12.2.6 output compare and time base interrupt on overflow, the ovf flag of the artcsr register is set and an overflow interrupt request is generated if the overflow interrupt enable bit, oie, in the artcsr register, is set. the ovf flag must be reset by the user software. this interrupt can be used as a time base in the application. 12.2.7 external clock and event detector mode using the f ext external prescaler input clock, the auto-reload timer can be used as an external clock event detector. in this mode, the artarr register is used to select the n event number of events to be counted before setting the ovf flag. n event = 256 - artarr caution: the external clock function is not available in halt mode. if halt mode is used in the application, prior to executing the halt instruction, the counter must be disabled by clearing the tce bit in the artcsr register to avoid spurious counter increments. duty cycle register auto-reload register pwmx output t 255 000 with oex=1 and opx=0 (artarr) (pwmdcrx) with oex=1 and opx=1 counter counter pwmx output t with oex=1 and opx=0 fdh feh ffh fdh feh ffh fdh feh ocrx=fch ocrx=fdh ocrx=feh ocrx=ffh artarr = fdh f counter
st72321xx-auto pwm auto-reload timer (art) doc id 13829 rev 1 91/243 figure 39. external event detector example (3 counts) 12.2.8 input capture function this mode allows the measurement of external signal pulse widths through articrx registers. each input capture can generate an interrupt independently on a selected input signal transition. this event is flagged by a set of the corresponding cfx bits of the input capture control/status register (articcsr). these input capture interrupts are enabled through the ciex bits of the articcsr register. the active transition (falling or rising edge) is software progra mmable through the csx bits of the articcsr register. the read only input capture registers (articrx) are used to latch the auto-reload counter value when a transition is detected on the arti cx pin (cfx bit set in articcsr register). after fetching the interrupt vector, the cfx flags can be read to identify the interrupt source. note: after a capture detection, data transfer in the articrx register is inhibited until it is read (clearing the cfx bit). the timer interrupt remains pendi ng while the cfx flag is set when the interrupt is enabled (ciex bit set). this means that the articrx register has to be read at each capture event to clear the cfx flag. the timing resolution is given by auto-reload coun ter cycle time (1/f counter ). note: during halt mode, if both the input capture and the external clock are enabled, the articrx register value is not guaranteed if the input capture pin and the external clock change simultaneously. counter t fdh feh ffh fdh ovf artcsr read interrupt artarr = fdh f ext =f counter feh ffh fdh if oie = 1 interrupt if oie = 1 artcsr read
pwm auto-reload timer (art) st72321xx-auto 92/243 doc id 13829 rev 1 12.2.9 external in terrupt capability this mode allows the in put capture capabilities to be used as external interrupt sources. the interrupts are generated on the edge of the articx signal. the edge sensitivity of the external interrupts is programmable (csx bit of articcsr register) and they are independently enabled through ciex bits of the articcsr register. after fetching the interrupt vector, the cfx flags can be read to identify the interrupt source. during halt mode, the external interrupts can be used to wake up the micro (if the ciex bit is set). figure 40. input capture timing diagram 04h counter t 01h f counter xxh 02h 03h 05h 06h 07h 04h articx pin cfx flag icrx register interrupt
st72321xx-auto pwm auto-reload timer (art) doc id 13829 rev 1 93/243 12.3 art registers 12.3.1 control/status register (artcsr) artcsr reset value: 0000 0000 (00h) 76543210 excl cc[2:0] tce fcrl oie ovf rw rw rw rw rw rw table 45. artcsr register description bit name function 7 excl external clock this bit is set and cleared by software. it selects the input clock for the 7-bit prescaler. 0: cpu clock 1: external clock 6:4 cc[2:0] counter clock control these bits are set and cleared by software. they determine the prescaler division ratio from f input (see ta b l e 4 6 ). 3tce timer counter enable this bit is set and cleared by software. it puts the timer in the lowest power consumption mode. 0: counter stopped (prescaler and counter frozen) 1: counter running 2 fcrl force counter re-load this bit is write-only and any attempt to re ad it will yield a logical zero. when set, it causes the contents of artarr register to be loaded into the counter, and the content of the prescaler register to be cleared in order to initialize the timer before starting to count. 1oie overflow interrupt enable this bit is set and cleared by software. it allows to enable/disable the interrupt which is generated when the ovf bit is set. 0: overflow interrupt disable 1: overflow interrupt enable 0ovf overflow flag this bit is set by hardware and cleared by software reading the artcsr register. it indicates the transition of the counter from ffh to the artarr value. 0: new transition not yet reached 1: transition reached table 46. prescaler selection for art f counter with f input = 8 mhz cc2 cc1 cc0 f input 8 mhz 000 f input / 2 4 mhz 0 0 1 f input / 4 2 mhz 0 1 0
pwm auto-reload timer (art) st72321xx-auto 94/243 doc id 13829 rev 1 12.3.2 counter access register (artcar) 12.3.3 auto-reload register (artarr) this register has two pwm management functions: ? adjusting the pwm frequency ? setting the pwm duty cycle resolution f input / 8 1 mhz 0 1 1 f input / 16 500 khz 1 0 0 f input / 32 250 khz 1 0 1 f input / 64 125 khz 1 1 0 f input / 128 62.5 khz 1 1 1 table 46. prescaler selection for art (continued) f counter with f input = 8 mhz cc2 cc1 cc0 artcar reset value: 0000 0000 (00h) 76543210 ca[7:0] rw table 47. artcar register description bit name function 7:0 ca[7:0] counter access data these bits can be set and cleared either by hardware or by software. the artcar register is used to read or wr ite the auto-reload counter ?on the fly? (while it is counting). artarr reset value: 0000 0000 (00h) 76543210 ar[7:0] rw table 48. artaar register description bit name function 7:0 ar[7:0] counter auto-reload data these bits are set and cleared by software. they are used to hold the auto-reload value which is automatically loaded in the counter when an overflow occurs. at the same time, the pwm output levels are changed according to the corresponding opx bit in the pwmcr register.
st72321xx-auto pwm auto-reload timer (art) doc id 13829 rev 1 95/243 12.3.4 pwm control register (pwmcr) table 49. pwm frequency versus resolution artarr value resolution f pwm min max 0 8-bit ~0.244 khz 31.25 khz [ 0..127 ] > 7-bit ~0.244 khz 62.5 khz [ 128..191 ] > 6-bit ~0.488 khz 125 khz [ 192..223 ] > 5-bit ~0.977 khz 250 khz [ 224..239 ] > 4-bit ~1.953 khz 500 khz pwmcr reset value: 0000 0000 (00h) 76543210 oe[3:0] op[3:0] rw rw table 50. pwmcr register description bit name function 7:4 oe[3:0] pwm output enable these bits are set and cleared by software. they enable or disable the pwm output channels independently acting on the corresponding i/o pin. 0: pwm output disabled 1: pwm output enabled 3:0 op[3:0] pwm output polarity these bits are set and cleared by software. they independently select the polarity of the four pwm output signals (see ta bl e 5 1 ). table 51. pwm output signal polarity selection pwmx output level opx (1) 1. when an opx bit is modified, the pwmx out put signal polarity is immediately reversed. counter <= ocrx counter > ocrx 100 011
pwm auto-reload timer (art) st72321xx-auto 96/243 doc id 13829 rev 1 12.3.5 duty cycle registers (pwmdcrx) a pwmdcrx register is associated with the ocrx register of each pwm channel to determine the second edge location of the pwm signal (the first edge location is common to all channels and given by the artarr register). these pwmdcr registers allow the duty cycle to be set independently for each pwm channel. 12.3.6 input capture control / status register (articcsr) pwmdcrx reset value: 0000 0000 (00h) 76543210 dc[7:0] rw table 52. pwmdcrx register description bit name function 7:0 dc[7:0] duty cycle data these bits are set and cleared by software. articcsr reset value: 0000 0000 (00h) 76543210 reserved cs[2:1] cie[2:1] cf[2:1] -rwrwrw table 53. articcsr register description bit name function 7:6 - reserved, always read as 0. 5:4 cs[2:1] capture sensitivity these bits are set and cleared by software. they determine the trigger event polarity on the corresponding input capture channel. 0: falling edge triggers capture on channel x 1: rising edge triggers capture on channel x 3:2 cie[2:1] capture interrupt enable these bits are set and cleared by software. they enable or disable the input capture channel interrupts independently. 0: input capture channel x interrupt disabled 1: input capture channel x interrupt enabled 1:0 cf[2:1] capture flag these bits are set by hardware and cleared by software reading the corresponding articr x register. each cfx bit indicates that an input capture x has occurred. 0: no input capture on channel x 1: an input capture has occurred on channel x.
st72321xx-auto pwm auto-reload timer (art) doc id 13829 rev 1 97/243 12.3.7 input capture registers (articrx) articrx reset value: 0000 0000 (00h) 76543210 ic[7:0] ro table 54. articrx register description bit name function 7:0 ic[7:0] input capture data these read only bits are set and cleared by hardware. an articrx register contains the 8-bit auto-reload counter value transferred by the input capture channel x event. table 55. pwm auto-reload timer register map and reset values address (hex.) register label 7 6 5 4 3 2 1 0 0073h pwmdcr3 reset value dc7 0 dc6 0 dc5 0 dc4 0 dc3 0 dc2 0 dc1 0 dc0 0 0074h pwmdcr2 reset value dc7 0 dc6 0 dc5 0 dc4 0 dc3 0 dc2 0 dc1 0 dc0 0 0075h pwmdcr1 reset value dc7 0 dc6 0 dc5 0 dc4 0 dc3 0 dc2 0 dc1 0 dc0 0 0076h pwmdcr0 reset value dc7 0 dc6 0 dc5 0 dc4 0 dc3 0 dc2 0 dc1 0 dc0 0 0077h pwmcr reset value oe3 0 oe2 0 oe1 0 oe0 0 op3 0 op2 0 op1 0 op0 0 0078h artcsr reset value excl 0 cc2 0 cc1 0 cc0 0 tce 0 fcrl 0 rie 0 ovf 0 0079h artcar reset value ca7 0 ca6 0 ca5 0 ca4 0 ca3 0 ca2 0 ca1 0 ca0 0 007ah artarr reset value ar7 0 ar6 0 ar5 0 ar4 0 ar3 0 ar2 0 ar1 0 ar0 0 007bh articcsr reset value 0 0 cs2 0 cs1 0 cie2 0 cie1 0 cf2 0 cf1 0 007ch articr1 reset value ic7 0 ic6 0 ic5 0 ic4 0 ic3 0 ic2 0 ic1 0 ic0 0 007dh articr2 reset value ic7 0 ic6 0 ic5 0 ic4 0 ic3 0 ic2 0 ic1 0 ic0 0
16-bit timer st72321xx-auto 98/243 doc id 13829 rev 1 13 16-bit timer 13.1 introduction the timer consists of a 16-bit free-running counter driven by a programmable prescaler. it may be used for a variety of purposes, including pulse length measurement of up to two input signals (input capture) or generation of up to two output waveforms (output compare and pwm). pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the cpu clock prescaler. some st7 devices have two on-chip 16-bit timers. they are completely independent, and do not share any resources. they are synchronized after an mcu reset as long as the timer clock frequencies are not modified. this description covers one or two 16-bit timers. in st7 devices with two timers, register names are prefixed with ta (timer a) or tb (timer b). 13.2 main features programmable prescaler: f cpu divided by 2, 4 or 8 overflow status flag and maskable interrupt external clock input (must be at least four times slower than the cpu clock speed) with the choice of active edge 1 or 2 output compare functions each with: ? 2 dedicated 16-bit registers ? 2 dedicated programmable signals ? 2 dedicated status flags ? 1 dedicated maskable interrupt 1 or 2 input capture functions each with: ? 2 dedicated 16-bit registers ? 2 dedicated active edge selection signals ? 2 dedicated status flags ? 1 dedicated maskable interrupt pulse width modulation mode (pwm) one pulse mode reduced power mode 5 alternate functions on i/o ports (icap1, icap2, ocmp1, ocmp2, extclk) (a) the block diagram is shown in figure 41 . note: when reading an input signal on a non- bonded pin, the value will always be ?1?. a. some timer pins may not be avai lable (not bonded) in some st7 dev ices. refer to the device pinout description.
st72321xx-auto 16-bit timer doc id 13829 rev 1 99/243 13.3 functional description 13.3.1 counter the main block of the programmable timer is a 16-bit free running upcounter and its associated 16-bit registers. the 16-bit registers are made up of two 8-bit registers called high and low. counter register (cr) counter high register (chr) is the most significant byte (ms byte) counter low register (clr) is the least significant byte (ls byte) alternate counter register (acr) alternate counter high register (achr) is the most significant byte (ms byte) alternate counter low register (aclr) is the least significant byte (ls byte) these two read-only 16-bit registers contain the same value but with the difference that reading the aclr register does not clear the tof bit (timer overflow flag), located in the status register (sr) (see note at the end of paragraph entitled 16-bit read sequence ). writing in the clr register or aclr register resets the free running counter to the fffch value. both counters have a reset value of fffch (this is the only value which is reloaded in the 16-bit timer). the reset value of both counters is also fffch in one pulse mode and pwm mode. the timer clock depends on the clock control bi ts of the cr2 register, as illustrated in table 61: timer clock selection . the value in the counter register repeats every 131072, 262144 or 524288 cpu clock cycles depending on the cc[1:0] bits. the timer frequency can be f cpu /2, f cpu /4, f cpu /8 or an external frequency.
16-bit timer st72321xx-auto 100/243 doc id 13829 rev 1 figure 41. timer block diagram 1. if ic, oc and to interrupt request have separate vectors, then t he last or is not present (see device interrupt vector table) . mcu-peripheral interface counter alternate output compare register output compare edge detect overflow detect circuit 1/2 1/4 1/8 8-bit buffer st7 internal bus latch1 ocmp1 icap1 extclk f cpu timer interrupt icf2 icf1 timd 0 0 ocf2 ocf1 tof pwm oc1e exedg iedg2 cc0 cc1 oc2e opm folv2 icie olvl1 iedg1 olvl2 folv1 ocie toie icap2 latch2 ocmp2 8 8 8 low 16 8 high 16 16 16 16 (control register 1) cr1 (control register 2) cr2 6 16 8 8 8 8 8 8 high low high high high low low low exedg timer internal bus circuit1 edge detect circuit2 circuit 1 output compare register 2 input capture register 1 input capture register 2 cc[1:0] counter pin pin pin pin pin register register (1) csr (control/status register)
st72321xx-auto 16-bit timer doc id 13829 rev 1 101/243 16-bit read sequence the 16-bit read sequence (from either the counter register or the alternate counter register) is illustrated in figure 42 . figure 42. 16-bit read sequence the user must read the ms byte first; the ls byte value is then buffered automatically. this buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the ms byte several times. after a complete reading sequence, if only the clr register or aclr register are read, they return the ls byte of the count value at the time of the read. whatever timer mode is used (input capture, output compare, one pulse mode or pwm mode) an overflow occurs when the counter rolls over from ffffh to 0000h, after which the tof bit of the sr register is set a timer interrupt is generated if ? the toie bit of the cr1 register is set and ? the i bit of the cc register is cleared if one of these conditions is false, the interr upt remains pending to be issued as soon as they are both true. clearing the overflow interrupt request is done in two steps: 1. reading the sr register while the tof bit is set 2. an access (read or write) to the clr register note: the tof bit is not cleared by accesses to aclr register. the advantage of accessing the aclr register rather than the clr register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the tof bit erroneously. the timer is not affected by wait mode. in halt mode, the counter stops counting until the mode is exited. counting then resumes from the previous count (mcu awakened by an interrupt) or from the reset count (mcu awakened by a reset). is buffered read at t0 read returns the buffered ls byte value at t0 at t0 +dt other instructions beginning of the sequence sequence completed ls byte ls byte ms byte
16-bit timer st72321xx-auto 102/243 doc id 13829 rev 1 13.3.2 external clock the external clock (where available) is selected if cc0 = 1 and cc1 = 1 in the cr2 register. the status of the exedg bit in the cr2 register determines the type of level transition on the external clock pin extclk that will trigger the free running counter. the counter is synchronize d with the falling edge of the internal cpu clock. a minimum of four falling edges of the cpu clock must occur betw een two consecutive active edges of the external clock; thus, the external clock frequency must be less than a quarter of the cpu clock frequency. figure 43. counter timing diagram, internal clock divided by 2 figure 44. counter timing diagram, internal clock divided by 4 figure 45. counter timing diagram, internal clock divided by 8 note: the mcu is in reset state when the internal reset signal is high; when it is low the mcu is running. cpu clock fffd fffe ffff 0000 0001 0002 0003 internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000 0001 cpu clock internal reset timer clock counter register timer overflow flag (tof) cpu clock internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000
st72321xx-auto 16-bit timer doc id 13829 rev 1 103/243 13.3.3 input capture in this section, the index, i , may be 1 or 2 because there are two input capture functions in the 16-bit timer. the two 16-bit input capture registers (ic1r and ic2r) are used to latch the value of the free running counter after a transition is detected on the icap i pin (see figure 46 ). ic i r register is a read-only register. the active transition is software programmable through the iedg i bit of control registers (cr i ). timing resolution is one count of the free running counter: (f cpu /cc[1:0]). procedure: to use the input capture function select the following in the cr2 register: select the timer clock (cc[1:0]) (see table 61: timer clock selection ). select the edge of the active transition on the icap2 pin with the iedg2 bit (the icap2 pin must be configured as floating input or input with pull-up without interrupt if this configuration is available). and select the following in the cr1 register: set the icie bit to generate an interrupt after an input capture coming from either the icap1 pin or the icap2 pin select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1pin must be configured as floating input or input with pull-up without interrupt if this configuration is available). when an input capture occurs: icf i bit is set. the ic i r register contains the value of the free running counter on the active transition on the icap i pin (see figure 47 ). a timer interrupt is generated if the icie bit is set and the i bit is cleared in the cc register. otherwise, the interrupt remains pending until both conditions become true. clearing the input capture interrupt request (that is, clearing the icf i bit) is done in two steps: 1. reading the sr register while the icf i bit is set 2. an access (read or write) to the ic i lr register note: 1 after reading the icihr regist er, transfer of input capture data is inhibited and icfi will never be set until the icilr register is also read. 2 the icir register contains the free running counter value which corresponds to the most recent input capture. 3 the two input capture functions can be used together even if the timer also uses the two output compare functions. 4 in one pulse mode and pwm mode only input capture 2 can be used. ms byte ls byte icir ic i hr ic i lr
16-bit timer st72321xx-auto 104/243 doc id 13829 rev 1 5 the alternate inputs (icap1 and icap2) are always directly connected to the timer. so any transitions on these pins activates the input capture function. 6 moreover if one of the icapi pins is configured as an input and the second one as an output, an interrupt can be generated if the user toggles the output pin and if the icie bit is set. 7 this can be avoided if the input capture function i is disabled by reading the icihr (see note 1). 8 the tof bit can be used with interrupt generation in order to measure events that go beyond the timer range (ffffh). figure 46. input capture block diagram figure 47. input capture timing diagram icie cc0 cc1 16-bit free running counter iedg1 (control register 1) cr1 (control register 2) cr2 icf2 icf1 0 0 0 (status register) sr iedg2 icap1 icap2 edge detect circuit2 16-bit ic1r register ic2r register edge detect circuit1 pin pin ff01 ff02 ff03 ff03 timer clock counter register icapi pin icapi flag icapi register note: the rising edge is the a ctive edge.
st72321xx-auto 16-bit timer doc id 13829 rev 1 105/243 13.3.4 output compare in this section, the index, i , may be 1 or 2 because there are two output compare functions in the 16-bit timer. this function can be used to control an output waveform or indicate when a period of time has elapsed. when a match is found between the output compare register and the free running counter, the output compare function: assigns pins with a programmable value if the oc i e bit is set sets a flag in the status register generates an interrupt if enabled two 16-bit registers output compare register 1 (oc1r) and output compare register 2 (oc2r) contain the value to be compared to the counter register each timer clock cycle. these registers are readable and writable and are not affected by the timer hardware. a reset event changes the oc i r value to 8000h. timing resolution is one count of the free running counter: (f cpu/cc[1:0] ). procedure to use the output compare function, select the following in the cr2 register: set the oc i e bit if an output is needed then the ocmp i pin is dedicated to the output compare i signal. select the timer clock (cc[1:0]) (see table 61: timer clock selection ). and select the following in the cr1 register: select the olvl i bit to applied to the ocmp i pins after the match occurs. set the ocie bit to generate an interrupt if it is needed. when a match is found between ocri register and cr register: ocf i bit is set. the ocmp i pin takes olvl i bit value (ocmp i pin latch is forced low during reset). a timer interrupt is generated if the ocie bit is set in the cr1 register and the i bit is cleared in the cc register (cc). the oc i r register value required for a specific timing application can be calculated using the following formula: where: ? t = output compare period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depending on cc[1:0] bits; see ta bl e 6 1 : timer clock selection ) ms byte ls byte oc i roc i hr oc i lr ? oc i r = ? t * f cpu presc
16-bit timer st72321xx-auto 106/243 doc id 13829 rev 1 if the timer clock is an external clock, the formula is: where: ? t = output compare period (in seconds) f cpu = external timer clock frequency (in hertz) clearing the output compare interrupt request (that is, clearing the ocf i bit) is done by: 1. reading the sr register while the ocf i bit is set 2. an access (read or write) to the oc i lr register the following procedure is recommended to prevent the ocf i bit from being set between the time it is read and the write to the oc i r register: write to the oc i hr register (further compares are inhibited). read the sr register (first step of the clearance of the ocf i bit, which may be already set). write to the oc i lr register (enables the output compare function and clears the ocf i bit). note: 1 after a processor write cycle to the ocihr r egister, the output compar e function is inhibited until the ocilr regist er is also written. 2 if the ocie bit is not set, the ocmpi pin is a general i/o port and the olvli bit will not appear when a match is found but an interrupt could be generated if the ocie bit is set. 3 in both internal and external clock modes, ocfi and ocmpi are set while the counter value equals the ocir register value (see figure 49 on page 107 for an example with f cpu /2 and figure 50 on page 107 for an example with f cpu /4). this behavior is the same in opm or pwm mode. 4 the output compare functions can be used both for generating external events on the ocmpi pins even if the input capture mode is also used. 5 the value in the 16-bit oc i r register and the olvi bit should be changed after each successful comparison in order to control an output waveform or establish a new elapsed timeout. 13.3.5 forced compare output capability when the folv i bit is set by software, the olvl i bit is copied to the ocmp i pin. the olv i bit has to be toggled in order to toggle the ocmp i pin when it is enabled (oc i e bit = 1). the ocf i bit is then not set by hardware, and thus no interrupt request is generated. the folvl i bits have no effect in both one pulse mode and pwm mode. ? oc i r = ? t * f ext
st72321xx-auto 16-bit timer doc id 13829 rev 1 107/243 figure 48. output compare block diagram figure 49. output compare timing diagram, f timer =f cpu /2 figure 50. output compare timing diagram, f timer =f cpu /4 output compare 16-bit circuit oc1r register 16-bit free running counter oc1e cc0 cc1 oc2e olvl1 olvl2 ocie (control register 1) cr1 (control register 2) cr2 0 0 0 ocf2 ocf1 (status register) sr 16-bit 16-bit ocmp1 ocmp2 latch 1 latch 2 oc2r register pin pin folv2 folv1 internal cpu clock timer clock counter register output compare register i (ocr i ) output compare flag i (ocf i ) ocmp i pin (olvl i =1) 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf internal cpu clock timer clock counter register output compare register i (ocr i ) 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf output compare flag i (ocf i ) ocmp i pin (olvl i =1)
16-bit timer st72321xx-auto 108/243 doc id 13829 rev 1 13.3.6 one pulse mode one pulse mode enables the generation of a pulse when an external event occurs. this mode is selected via the opm bit in the cr2 register. the one pulse mode uses the input capture1 function and the output compare1 function. procedure to use one pulse mode: 1. load the oc1r register with the value corresponding to the length of the pulse (using the appropriate formula below according to the timer clock source used). 2. select the following in the cr1 register: ? using the olvl1 bit, select the level to be applied to the ocmp1 pin after the pulse. ? using the olvl2 bit, select the level to be applied to the ocmp1 pin during the pulse. ? select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1 pin must be configured as floating input). 3. select the following in the cr2 register: ? set the oc1e bit, the ocmp1 pin is then dedicated to the output compare 1 function. ? set the opm bit. ? select the timer clock cc[1:0] (see table 61: timer clock selection ). then, on a valid event on the icap1 pin, the counter is initialized to fffch and olvl2 bit is loaded on the ocmp1 pin, the icf1 bit is set and the value fffdh is loaded in the ic1r register. figure 51. one pulse mode cycle flowchart because the icf1 bit is set when an active edge occurs, an interrupt can be generated if the icie bit is set. clearing the input capture interrupt request (that is, clearing the icf i bit) is done in two steps: 1. reading the sr register while the icf i bit is set 2. an access (read or write) to the ic i lr register ocmp1 = olvl1 when counter = oc1r when event occurs ocmp1 = olvl2 counter is reset to fffch icf1 bit is set icr1 = counter on icap1
st72321xx-auto 16-bit timer doc id 13829 rev 1 109/243 the oc1r register value required for a specif ic timing application can be calculated using the following formula: where: t = pulse period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depending on the cc[1:0] bits; see table 61: timer clock selection ) if the timer clock is an external clock the formula is: where: t = pulse period (in seconds) f ext = external clock frequency (in hertz) when the value of the counter is equal to the value of the contents of the oc1r register, the olvl1 bit is output on the ocmp1 pin (see figure 52 ). note: 1 the ocf1 bit cannot be set by hardware in one pulse mode but the ocf2 bit can generate an output compare interrupt. 2 when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. 3 if olvl1 = olvl2 a continuous sig nal will be seen on the ocmp1 pin. 4 the icap1 pin cannot be used to perform input capture. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the icap1 pin and icf1 can also generates interrupt if icie is set. 5 when one pulse mode is used oc1r is dedic ated to this mode. nevertheless oc2r and ocf2 can be used to indicate a period of time has been elapsed but cannot generate an output waveform because the level olvl2 is dedicated to the one pulse mode. figure 52. one pulse mode timing example oc i r value = t * f cpu presc - 5 oc i r = t * f ext - 5 counter fffc fffd fffe 2ed0 2ed1 2ed2 2ed3 fffc fffd olvl2 olvl2 olvl1 icap1 ocmp1 compare1 note: iedg1 = 1, oc1r = 2ed0h, olvl1 = 0, olvl2 = 1 01f8 01f8 2ed3 ic1r
16-bit timer st72321xx-auto 110/243 doc id 13829 rev 1 figure 53. pulse width modulation mode timing example with 2 output compare functions note: on timers with only one output compare register, a fixed frequency pwm signal can be generated using the output compare and the counter overflow to define the pulse length. 13.3.7 pulse width modulation mode pulse width modulation (pwm) mode enables the generation of a signal with a frequency and pulse length determined by the value of the oc1r and oc2r registers. pulse width modulation mode uses the complete output compare 1 function plus the oc2r register, and so this functionality cannot be used when pwm mode is activated. in pwm mode, double buffering is implemented on the output compare registers. any new values written in the oc1r and oc2r registers are taken into account only at the end of the pwm period (oc2) to avoid spikes on the pwm output pin (ocmp1). procedure to use pulse width modulation mode: 1. load the oc2r register with the value corresponding to the period of the signal using the appropriate formula below according to the timer clock source used. 2. load the oc1r register with the value corresponding to the period of the pulse if olvl1 = 0 and olvl2 = 1 using the appropriate formula below according to the timer clock source used. 3. select the following in the cr1 register: ? using the olvl1 bit, select the level to be applied to the ocmp1 pin after a successful comparison with the oc1r register. ? using the olvl2 bit, select the level to be applied to the ocmp1 pin after a successful comparison with the oc2r register. 4. select the following in the cr2 register: ? set oc1e bit: the ocmp1 pin is then dedicated to the output compare 1 function. ? set the pwm bit. ? select the timer clock (cc[1:0]) (see table 61: timer clock selection ). counter 34e2 34e2 fffc olvl2 olvl2 olvl1 ocmp1 compare2 compare1 compare2 note: oc1r = 2ed0h, oc2r = 34e2, olvl1 = 0, olvl2 = 1 fffc fffd fffe 2ed0 2ed1 2ed2
st72321xx-auto 16-bit timer doc id 13829 rev 1 111/243 figure 54. pulse width modulation cycle flowchart if olvl1 = 1 and olvl2 = 0 the length of the positive pulse is the difference between the oc2r and oc1r registers. if olvl1 = olvl2 a continuous signal will be seen on the ocmp1 pin. the oc i r register value required for a specific timing application can be calculated using the following formula: where: t = signal or pulse period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depending on cc[1:0] bits; see ta bl e 6 1 : timer clock selection ) if the timer clock is an external clock the formula is: where: t = signal or pulse period (in seconds) f ext = external timer clock frequency (in hertz) the output compare 2 event causes the counter to be initialized to fffch (see figure 53 ). note: 1 after a write instruction to the ocihr register, the output co mpare function is inhibited until the ocilr register is also written. 2 the ocf1 and ocf2 bits cannot be set by hardware in pwm mode therefore the output compare interrupt is inhibited. 3 the icf1 bit is set by hardware when the c ounter reaches the oc2r value and can produce a timer interrupt if the icie bit is set and the i bit is cleared. 4 in pwm mode the icap1 pin cannot be used to perform input capture because it is disconnected to the timer. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset each period and icf1 can also generates interrupt if icie is set. 5 when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. counter ocmp1 = olvl2 counter = oc2r ocmp1 = olvl1 when when = oc1r counter is reset to fffch icf1 bit is set oc i r value = t * f cpu presc - 5 oc i r = t * f ext -5
16-bit timer st72321xx-auto 112/243 doc id 13829 rev 1 13.4 low power modes 13.5 interrupts note: the 16-bit timer interrupt events are connected to the same interrupt vector (see chapter 7: interrupts on page 49 ). these events generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is rese t (rim instruction). 13.6 summary of timer modes table 56. effect of low power modes on 16-bit timer mode effect wait no effect on 16-bit timer. timer interrupts cause the device to exit from wait mode. halt 16-bit timer registers are frozen. in halt mode, the counter stops counting until halt mode is exited. counting resumes from the previous count when the mcu is woken up by an interrupt with ?exit from halt mode? capability or from the counter reset va lue when the mcu is woken up by a reset. if an input capture event occurs on the icap i pin, the input capture detection circuitry is armed. consequently, when the mcu is woken up by an interrupt with ?exit from halt mode? capability, the icf i bit is set, and the counter value present when exiting from halt mode is captured into the ic i r register. table 57. 16-bit timer interrupt control/wake-up capability interrupt event event flag enable control bit exit from wait exit from halt input capture 1 event/counter reset in pwm mode icf1 icie ye s n o input capture 2 event icf2 output compare 1 event (not available in pwm mode) ocf1 ocie output compare 2 event (not available in pwm mode) ocf2 timer overflow event tof toie table 58. timer modes modes timer resources input capture 1 input capture 2 output compare 1 output compare 2 input capture (1 and/or 2) yes yes yes yes output compare (1 and/or 2)
st72321xx-auto 16-bit timer doc id 13829 rev 1 113/243 13.7 16-bit timer registers each timer is associated with 3 control and status registers, and with 6 pairs of data registers (16-bit values) relating to the 2 input captures, the 2 output compares, the counter and the alternate counter. 13.7.1 control register 1 (cr1) one pulse mode no not recommended (1) no partially (2) pwm mode not recommended (3) no 1. see note 4 in section 13.3.6 one pulse mode 2. see note 5 in section 13.3.6 one pulse mode 3. see note 4 in section 13.3.7 pulse width modulation mode table 58. timer modes modes timer resources input capture 1 input capture 2 output compare 1 output compare 2 cr1 reset value: 0000 0000 (00h) 76543210 icie ocie toie folv2 folv1 olvl2 iedg1 olvl1 rw rw rw rw rw rw rw rw table 59. cr1 register description bit name function 7icie input capture interrupt enable 0: interrupt is inhibited 1: a timer interrupt is generated whenever the icf1 or icf2 bit of the sr register is set. 6ocie output compare interrupt enable 0: interrupt is inhibited 1: a timer interrupt is generated whenever th e ocf1 or ocf2 bit of the sr register is set. 5 toie timer overflow interrupt enable 0: interrupt is inhibited 1: a timer interrupt is enabled whenever the tof bit of the sr register is set. 4folv2 forced output compare 2 this bit is set and cleared by software. 0: no effect on the ocmp2 pin 1: forces the olvl2 bit to be copied to the ocmp2 pin, if the oc2e bit is set and even if there is no successful comparison
16-bit timer st72321xx-auto 114/243 doc id 13829 rev 1 13.7.2 control register 2 (cr2) 3folv1 forced output compare 1 this bit is set and cleared by software. 0: no effect on the ocmp1 pin 1: forces olvl1 to be copied to the ocmp1 pin, if the oc1e bit is set and even if there is no successful comparison 2olvl2 output level 2 this bit is copied to the ocmp2 pin whenever a successful comparison occurs with the oc2r register and ocxe is set in the cr2 register. this value is copied to the ocmp1 pin in one pulse mode and pulse width modulation mode. 1iedg1 input edge 1 this bit determines which type of level transition on the icap1 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. 0olvl1 output level 1 the olvl1 bit is copied to the ocmp1 pin whenever a successful comparison occurs with the oc1r register and the oc1e bit is set in the cr2 register. table 59. cr1 register description (continued) bit name function cr2 reset value: 0000 0000 (00h) 76543210 oc1e oc2e opm pwm cc[1:0] iedg2 exedg rw rw rw rw rw rw rw table 60. cr2 register description bit name function 7oc1e output compare 1 pin enable this bit is used only to output the signal from the timer on the ocmp1 pin (olv1 in output compare mode, both olv1 and olv2 in pwm and one-pulse mode). whatever the value of the oc1e bit, t he output compare 1 function of the timer remains active. 0: ocmp1 pin alternate function disabled (i/o pin free for general-purpose i/o) 1: ocmp1 pin alternate function enabled 6oc2e output compare 2 pin enable this bit is used only to output the signal from the timer on the ocmp2 pin (olv2 in output compare mode). whatever the value of the oc2e bit, the output compare 2 function of the timer remains active. 0: ocmp2 pin alternate function disabled (i/o pin free for general-purpose i/o) 1: ocmp2 pin alternate function enabled
st72321xx-auto 16-bit timer doc id 13829 rev 1 115/243 13.7.3 control/status register (csr) 5opm one pulse mode 0: one pulse mode is not active. 1: one pulse mode is active, the icap1 pin can be used to trigger one pulse on the ocmp1 pin; the active transition is given by the iedg1 bit. the length of the generated pulse depends on the contents of the oc1r register. 4pwm pulse width modulation 0: pwm mode is not active. 1: pwm mode is active, the ocmp1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of oc1r register; the period depends on the value of oc2r register. 3:2 cc[1:0] clock control the timer clock mode depends on these bits (see ta bl e 6 1 ). 1iedg2 input edge 2 this bit determines which type of level transition on the icap2 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. 0 exedg external clock edge this bit determines which type of level tr ansition on the external clock pin extclk will trigger the counter register. 0: a falling edge triggers the counter register. 1: a rising edge triggers the counter register. table 61. timer clock selection timer clock cc1 cc0 f cpu / 4 0 0 f cpu / 2 0 1 f cpu / 8 1 0 external clock (where available) (1) 1. if the external clock pin is not available, programmi ng the external clock confi guration stops the counter. 11 table 60. cr2 register description (continued) bit name function csr reset value: xxxx x0xx (xxh) 76543210 icf1 ocf1 tof icf2 ocf2 timd reserved ro ro ro ro ro rw -
16-bit timer st72321xx-auto 116/243 doc id 13829 rev 1 13.7.4 input capture 1 hi gh register (ic1hr) this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). table 62. csr register description bit name function 7icf1 input capture flag 1 0: no input capture (reset value) 1: an input capture has occurred on the icap1 pin or the counter has reached the oc2r value in pwm mode. to clear this bi t, first read the sr register, then read or write the low byte of the ic1r (ic1lr) register. 6ocf1 output compare flag 1 0: no match (reset value) 1: the content of the free running counter has matched the content of the oc1r register. to clear this bit, first read the sr register, then read or write the low byte of the oc1r (oc1lr) register. 5tof timer overflow flag 0: no timer overflow (reset value) 1: the free running counter rolled over from ffffh to 0000h. to clear this bit, first read the sr register, then read or writ e the low byte of the cr (clr) register. note: reading or writing the aclr register does not clear tof. 4icf2 input capture flag 2 0: no input capture (reset value). 1: an input capture has occurred on the icap2 pin. to clear this bit, first read the sr register, then read or write the lo w byte of the ic2r (ic2lr) register. 3ocf2 output compare flag 2 0: no match (reset value) 1: the content of the free running counter has matched the content of the oc2r register. to clear this bit, first read the sr register, then read or write the low byte of the oc2r (oc2lr) register. 2timd timer disable this bit is set and cleared by software. when set, it freezes the timer prescaler and counter and disabled the output fu nctions (ocmp1 and ocmp2 pins) to reduce power consumption. access to the timer registers is still available, allowing the timer configuration to be changed, or th e counter reset, while it is disabled. 0: timer enabled 1: timer prescaler, counter and outputs disabled 1:0 - reserved, must be kept cleared ic1hr reset value: undefined 76543210 msb lsb ro ro ro ro ro ro ro ro
st72321xx-auto 16-bit timer doc id 13829 rev 1 117/243 13.7.5 input capture 1 low register (ic1lr) this is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 1 event). 13.7.6 output compare 1 high register (oc1hr) this is an 8-bit register that contains the high part of the value to be compared to the chr register. 13.7.7 output compare 1 low register (oc1lr) this is an 8-bit register that contains the low part of the value to be compared to the clr register. 13.7.8 output compare 2 high register (oc2hr) this is an 8-bit register that contains the high part of the value to be compared to the chr register. ic1lr reset value: undefined 76543210 msb lsb ro ro ro ro ro ro ro ro oc1hr reset value: 1000 0000 (80h) 76543210 msb lsb rw rw rw rw rw rw rw rw oc1lr reset value: 0000 0000 (00h) 76543210 msb lsb rw rw rw rw rw rw rw rw oc2hr reset value: 1000 0000 (80h) 76543210 msb lsb rw rw rw rw rw rw rw rw
16-bit timer st72321xx-auto 118/243 doc id 13829 rev 1 13.7.9 output compare 2 low register (oc2lr) this is an 8-bit register that contains the low part of the value to be compared to the clr register. 13.7.10 counter hi gh register (chr) this is an 8-bit register that contains the high part of the counter value. 13.7.11 counter low register (clr) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after accessing the csr register clears the tof bit. 13.7.12 alternate counter high register (achr) this is an 8-bit register that contains the high part of the counter value. oc2lr reset value: 0000 0000 (00h) 76543210 msb lsb rw rw rw rw rw rw rw rw chr reset value: 1111 1111 (ffh) 76543210 msb lsb ro ro ro ro ro ro ro ro clr reset value: 1111 1100 (fch) 76543210 msb lsb ro ro ro ro ro ro ro ro achr reset value: 1111 1111 (ffh) 76543210 msb lsb ro ro ro ro ro ro ro ro
st72321xx-auto 16-bit timer doc id 13829 rev 1 119/243 13.7.13 alternate counter low register (aclr) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after an access to csr register does not clear the tof bit in the csr register. 13.7.14 input capture 2 high register (ic2hr) this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 2 event). 13.7.15 input capture 2 low register (ic2lr) this is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 2 event). aclr reset value: 1111 1100 (fch) 76543210 msb lsb ro ro ro ro ro ro ro ro ic2hr reset value: undefined 76543210 msb lsb ro ro ro ro ro ro ro ro ic2lr reset value: undefined 76543210 msb lsb ro ro ro ro ro ro ro ro
16-bit timer st72321xx-auto 120/243 doc id 13829 rev 1 related documentation sci software communications using 16-bit timer (an 973) real-time clock with st7 timer output compare (an 974) driving a buzzer through the st7 timer pwm function (an 976) using st7 pwm signal to generate analog input (sinusoid) (an1041) uart emulation software (an1046) pwm duty cycle switch implementing true 0 or 100 per cent duty cycle (an1078) starting a pwm signal directly at high level using the st7 16-bit timer (an1504) table 63. 16-bit timer register map and reset values address (hex.) register label 76543210 timer a: 32 timer b: 42 cr1 reset value icie 0 ocie 0 toie 0 folv2 0 folv1 0 olvl2 0 iedg1 0 olvl1 0 timer a: 31 timer b: 41 cr2 reset value oc1e 0 oc2e 0 opm 0 pwm 0 cc1 0 cc0 0 iedg2 0 exedg 0 timer a: 33 timer b: 43 csr reset value icf1 x ocf1 x tof x icf2 x ocf2 x timd 0 - x - x timer a: 34 timer b: 44 ic1hr reset value msb xxxxxxx lsb x timer a: 35 timer b: 45 ic1lr reset value msb xxxxxxx lsb x timer a: 36 timer b: 46 oc1hr reset value msb 1000000 lsb 0 timer a: 37 timer b: 47 oc1lr reset value msb 0000000 lsb 0 timer a: 3e timer b: 4e oc2hr reset value msb 1000000 lsb 0 timer a: 3f timer b: 4f oc2lr reset value msb 0000000 lsb 0 timer a: 38 timer b: 48 chr reset value msb 1111111 lsb 1 timer a: 39 timer b: 49 clr reset value msb 1111110 lsb 0 timer a: 3a timer b: 4a achr reset value msb 1111111 lsb 1 timer a: 3b timer b: 4b aclr reset value msb 1111110 lsb 0 timer a: 3c timer b: 4c ic2hr reset value msb xxxxxxx lsb x timer a: 3d timer b: 4d ic2lr reset value msb xxxxxxx lsb x
st72321xx-auto serial peripheral interface (spi) doc id 13829 rev 1 121/243 14 serial peripheral interface (spi) 14.1 introduction the serial peripheral interface (spi) allows full-duplex, synchronous, serial communication with external devices. an spi system may consist of a master and one or more slaves however the spi interface cannot be a master in a multimaster system. 14.2 main features full duplex synchronous transfers (on 3 lines) simplex synchronous transfers (on 2 lines) master or slave operation 6 master mode frequencies (f cpu /4 max.) f cpu /2 max. slave mode frequency (see note) ss management by software or hardware programmable clock polarity and phase end of transfer interrupt flag write collision, master mo de fault and overrun flags note: in slave mode, continuous transmission is not possible at maximum frequency due to the software overhead for clearing status flags and to initiate the next transmission sequence. 14.3 general description figure 55 shows the serial peripheral interface (spi) block diagram. there are three registers: spi control register (spicr) spi control/status register (spicsr) spi data register (spidr) the spi is connected to external devices through four pins: miso (master in / slave out data) mosi (master out / slave in data) sck (serial clock out by spi masters and input by spi slaves) ss (slave select): this input signal acts as a ?chip select? to let the spi master communicate with slaves individually and to avoid contention on the data lines. slave ss inputs can be driven by standard i/o ports on the master mcu.
serial peripheral interface (spi) st72321xx-auto 122/243 doc id 13829 rev 1 figure 55. serial peripheral interface block diagram 14.3.1 functional description a basic example of interconnections between a single master and a single slave is illustrated in figure 56 . the mosi pins are connected together and the miso pins are connected together. in this way data is transferred serially between master and slave (most significant bit first). the communication is always initiated by th e master. when the master device transmits data to a slave device via mosi pin, the sl ave device responds by sending data to the master device via the miso pin. this implies full duplex communication with both data out and data in synchronized with the same clock signal (which is provided by the master device via the sck pin). to use a single data line, the miso and mosi pins must be connected at each node (in this case only simplex communication is possible). four possible data/clock timing relationships may be chosen (see figure 59 ) but master and slave must be programmed with the same timing mode. spidr read buffer 8-bit shift register write read data/address bus spi spie spe mstr cpha spr0 spr1 cpol serial clock generator mosi miso ss sck control state spicr spicsr interrupt request master control spr2 0 7 0 7 spif wcol modf 0 ovr ssi ssm sod sod bit ss 1 0
st72321xx-auto serial peripheral interface (spi) doc id 13829 rev 1 123/243 figure 56. single master/s ingle slave application 14.3.2 slave select management as an alternative to using the ss pin to control the slave select signal, the application can choose to manage the slave select signal by software. this is configured by the ssm bit in the spicsr register (see figure 58 ) in software management, the external ss pin is free for other application uses and the internal ss signal level is driven by writing to the ssi bit in the spicsr register. in master mode ss internal must be held high continuously in slave mode there are two cases depending on the data/clock timing relationship (see figure 57 ): if cpha = 1 (data latched on 2nd clock edge): ss internal must be held low during the entire transmission. this im plies that in single slave applications the ss pin either can be tied to v ss , or made free for standard i/o by managing the ss function by software (ssm = 1 and ssi = 0 in the in the spicsr register) if cpha = 0 (data latched on 1st clock edge): ss internal must be held low during byte transmission and pulled high between each byte to allow the slave to write to the shift register. if ss is not pulled high, a write collision error will occu r when the slave writes to the shift register (see write collision error (wcol) on page 128 ). 8-bit shift register spi clock generator 8-bit shift register miso mosi mosi miso sck sck slave master ss ss +5v msbit lsbit msbit lsbit not used if ss is managed by software
serial peripheral interface (spi) st72321xx-auto 124/243 doc id 13829 rev 1 figure 57. generic ss timing diagram figure 58. hardware/software slave select management 14.3.3 master mode operation in master mode, the serial clock is output on the sck pin. the clock frequency, polarity and phase are configured by software (refer to the description of the spicsr register). note: the idle state of sck must correspond to the polarity selected in the spicsr register (by pulling up sck if cpol = 1 or pulling down sck if cpol = 0). how to operate the spi in master mode to operate the spi in master mode, perform the following steps in order: 1. write to the spicr register: a) select the clock frequency by configuring the spr[2:0] bits. b) select the clock polarity and clock phase by configuring the cpol and cpha bits. figure 59 shows the four possible configurations. note: the slave must have the same cpol and cpha settings as the master. 2. write to the spicsr register: either set the ssm bit and set the ssi bit or clear the ssm bit and tie the ss pin high for the complete byte transmit sequence. 3. write to the spicr register: set the mstr and spe bits note: mstr and spe bits re main set only if ss is high). important : if the spicsr register is not written first, the spicr register setting (mstr bit) may not be taken into account. the transmit sequence begins when software writes a byte in the spidr register. mosi/miso master ss slave ss (if cpha=0) slave ss (if cpha=1) byte 1 byte 2 byte 3 1 0 ss internal ssm bit ssi bit ss external pin
st72321xx-auto serial peripheral interface (spi) doc id 13829 rev 1 125/243 14.3.4 master mode transmit sequence when software writes to the spidr register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the mosi pin most significant bit first. when data transfer is complete: ? the spif bit is set by hardware ? an interrupt request is generated if the spie bit is set and the interrupt mask in the ccr register is cleared. clearing the spif bit is performed by the following software sequence: 1. an access to the spicsr register while the spif bit is set 2. a read to the spidr register. note: while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read. 14.3.5 slave mode operation in slave mode, the serial clock is received on the sck pin from the master device. to operate the spi in slave mode: 1. write to the spicsr register to perform the following actions: a) select the clock polarity and clock phase by configuring the cpol and cpha bits (see figure 59 ). note: the slave must have the same cpol and cpha settings as the master. b) manage the ss pin as described in slave select management on page 123 and figure 57 . if cpha = 1, ss must be held low continuously. if cpha = 0, ss must be held low during byte transmission and pulled up between each byte to let the slave write in the shift register. 2. write to the spicr register to clear the mstr bit and se t the spe bit to enable the spi i/o functions. 14.3.6 slave mo de transmit sequence when software writes to the spidr register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the miso pin most significant bit first. the transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its mosi pin. when data transfer is complete: ? the spif bit is set by hardware. ? an interrupt request is generated if spie bit is set and interrupt mask in the ccr register is cleared. clearing the spif bit is performed by the following software sequence: 1. an access to the spicsr register while the spif bit is set 2. a write or a read to the spidr register note: while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read.
serial peripheral interface (spi) st72321xx-auto 126/243 doc id 13829 rev 1 the spif bit can be cleared during a second transmission; however, it must be cleared before the second spif bit in order to prevent an overrun condition (see overrun condition (ovr) on page 128 ). 14.4 clock phase and clock polarity four possible timing relationships may be chosen by software, using the cpol and cpha bits (see figure 59 ). note: the idle state of sck must correspond to the polarity selected in the spicsr register (by pulling up sck if cpol = 1 or pulling down sck if cpol = 0). the combination of the cpol clock polarity and cpha (clock phase) bits selects the data capture clock edge figure 59 shows an spi transfer with the four combinations of the cpha and cpol bits. the diagram may be interpreted as a master or slave timing diagram where the sck pin, the miso pin, the mosi pin are directly connected between the master and the slave device. note: if cpol is changed at the communication byte boundaries, the spi must be disabled by resetting the spe bit.
st72321xx-auto serial peripheral interface (spi) doc id 13829 rev 1 127/243 figure 59. data clock timing diagram msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit capture strobe cpha = 1 msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit capture strobe cpha = 0 note: this figure should not be used as a replacement for parametric information. refer to section 19: electrical characteristics . sck (cpol = 1) sck (cpol = 0) miso (from master) mosi (from slave) ss (to slave) sck (cpol = 1) sck (cpol = 0) miso (from master) mosi (from slave) ss (to slave)
serial peripheral interface (spi) st72321xx-auto 128/243 doc id 13829 rev 1 14.5 error flags 14.5.1 master mode fault (modf) master mode fault occurs when the master device has its ss pin pulled low. when a master mode fault occurs: the modf bit is set and an spi interrupt request is generated if the spie bit is set. the spe bit is reset. this blocks all output from the device and disables the spi peripheral. the mstr bit is reset, thus forcing the device into slave mode. clearing the modf bit is done through a software sequence: 1. a read access to the spicsr regi ster while the modf bit is set. 2. a write to the spicr register. note: to avoid any conflicts in an ap plication with multiple slaves, the ss pin must be pulled high during the modf bit clearing sequence. the spe and mstr bits may be restored to their original state during or after this clearing sequence. hardware does not allow the us er to set the spe and mstr bits while the modf bit is set except in the modf bit clearing sequence. 14.5.2 overrun condition (ovr) an overrun condition occurs, when the master device has sent a data byte and the slave device has not cleared the spif bit issued from the previously transmitted byte. when an overrun occurs: the ovr bit is set and an interrupt request is generated if the spie bit is set. in this case, the receiver buffer contains the byte sent after the spif bit was last cleared. a read to the spidr register returns this byte. all other bytes are lost. the ovr bit is cleared by reading the spicsr register. 14.5.3 write collision error (wcol) a write collision occurs when the software trie s to write to the spidr register while a data transfer is taking place with an external device. when this happens, the transfer continues uninterrupted; and the softwa re write will be unsuccessful. write collisions can occur both in master and slave mode. see also slave select management on page 123 . note: a ?read collision? will never occur since the re ceived data byte is placed in a buffer in which access is always synchronous with the mcu operation. the wcol bit in the spicsr register is set if a write collision occurs. no spi interrupt is generated when the wcol bit is set (the wcol bit is a status flag only). clearing the wcol bit is done through a software sequence (see figure 60 ).
st72321xx-auto serial peripheral interface (spi) doc id 13829 rev 1 129/243 figure 60. clearing the wcol bit (write collision flag) software sequence 14.5.4 single master systems a typical single master system may be configured, using an mcu as the master and four mcus as slaves (see figure 61 ). the master device selects the individual slave devices by using four pins of a parallel port to control the four ss pins of the slave devices. the ss pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices. note: to prevent a bus conflict on the miso line the master allows only one active slave device during a transmission. for more security, the slave device may respond to the master with the received data byte. then the master will receive the previous byte back from the slave device if all miso and mosi pins are connected and the slave has not written to its spidr register. other transmission security methods can use ports for handshake lines or data bytes with command fields. figure 61. single master / multiple slave configuration clearing sequence after spif = 1 (e nd of a data byte transfer) 1st step read spicsr read spidr 2nd step spif = 0 wcol = 0 clearing sequence before spif = 1 (during a data byte transfer) 1st step 2nd step wcol = 0 read spicsr read spidr note: writing to the spidr register instead of reading it does not reset the wcol bit. result result miso mosi mosi mosi mosi mosi miso miso miso miso ss ss ss ss ss sck sck sck sck sck 5v ports slave mcu slave mcu slave mcu slave mcu master mcu
serial peripheral interface (spi) st72321xx-auto 130/243 doc id 13829 rev 1 14.6 low power modes 14.6.1 using the spi to wake up the mcu from halt mode in slave configuration, the spi is able to wake up the st7 device from halt mode through a spif interrupt. the data received is subsequently read from the spidr register when the software is running (interrupt vector fetch). if multiple data transfers have been performed before software clears the spif bit, then the ovr bit is set by hardware. note: when waking up from halt mode, if the spi remains in slave mode, it is recommended to perform an extra communications cycle to bring the spi from halt mode state to normal state. if the spi exits from slave mode, it returns to normal state immediately. caution: the spi can wake up the st7 from halt mode only if the slave select signal (external ss pin or the ssi bit in the spicsr register) is low when the st7 enters halt mode. so if slave selection is configured as external (see slave select management on page 123 ), make sure the master drives a low level on the ss pin when the slave enters halt mode. 14.7 interrupts note: the spi interrupt events are connected to the same interrupt vector (see interrupts chapter). they generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). table 64. effect of low power modes on spi mode effect wait no effect on spi. spi interrupt events cause the device to exit from wait mode. halt spi registers are frozen. in halt mode, the spi is inactive. spi operation resumes when the mcu is woken up by an interrupt with ?exit from halt mode? c apability. the data received is subsequently read from the spidr register when the software is running (interrupt vector fetching). if several data are received before the wake-up event, then an overrun error is generated. this error can be detected after the fetch of the interrupt routine that woke up the device. table 65. spi interrupt control/wake-up capability interrupt event event flag enable control bit exit from wait exit from halt spi end of transfer event spif spie yes ye s master mode fault event modf no overrun error ovr
st72321xx-auto serial peripheral interface (spi) doc id 13829 rev 1 131/243 14.8 spi registers 14.8.1 control register (spicr) spicr reset value: 0000 xxxx (0xh) 76543210 spie spe spr2 mstr cpol cpha spr[1:0] rw rw rw rw rw rw rw table 66. spicr register description bit name function 7spie serial peripheral interrupt enable this bit is set and cleared by software. 0: interrupt is inhibited 1: an spi interrupt is generated whenever spif = 1, modf = 1 or ovr = 1 in the spicsr register. 6 spe serial peripheral output enable this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss = 0 (see master mode fault (modf) on page 128 ). the spe bit is cleared by reset, so the spi peripheral is not initially connected to the external pins. 0: i/o pins free for general purpose i/o 1: spi i/o pin alternate functions enabled 5spr2 divider enable this bit is set and cleared by software and is cleared by reset. it is used with the spr[1:0] bits to set the baud rate. refer to ta b l e 6 7 . 0: divider by 2 enabled 1: divider by 2 disabled note: this bit has no effect in slave mode. 4mstr master mode this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see master mode fault (modf) on page 128 ). 0: slave mode 1: master mode. the function of the sck pin changes from an input to an output and the functions of the miso and mosi pins are reversed. 3cpol clock polarity this bit is set and cleared by software. this bit determines the idle state of the serial clock. the cpol bit affects both the master and slave modes. 0: sck pin has a low level idle state 1: sck pin has a high level idle state note: if cpol is changed at the communi cation byte boundaries, the spi must be disabled by resetting the spe bit. 2cpha clock phase this bit is set and cleared by software. 0: the first clock transition is the first data capture edge. 1: the second clock transition is the first capture edge. note: the slave must have the same cp ol and cpha settings as the master.
serial peripheral interface (spi) st72321xx-auto 132/243 doc id 13829 rev 1 14.8.2 control/status register (spicsr) 1:0 spr[1:0] serial clock frequency these bits are set and cleared by software. used with the spr2 bit, they select the baud rate of the spi serial clock sck output by the spi in master mode. note: these 2 bits have no effect in slave mode. table 67. spi master mode sck frequency serial clock spr2 spr1 spr0 f cpu /4 100 f cpu /8 000 f cpu /16 001 f cpu /32 110 f cpu /64 010 f cpu /128 011 table 66. spicr register description (continued) bit name function spicsr reset value: 0000 0000 (00h) 76543210 spif wcol ovr modf reserved sod ssm ssi ro ro ro ro - rw rw rw table 68. spicsr register description bit name function 7spif serial peripheral data transfer flag this bit is set by hardware when a transfer has been completed. an interrupt is generated if spie = 1 in the spicr register. it is cleared by a software sequence (an access to the spicsr register followed by a write or a read to the spidr register). 0: data transfer is in progress or the flag has been cleared 1: data transfer between the device and an external device has been completed. while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read. 6wcol write collision status this bit is set by hardware when a write to the spidr register is done during a transmit sequence. it is cleared by a software sequence (see figure 60 ). 0: no write collision occurred. 1: a write collision has been detected. 5ovr spi overrun error this bit is set by hardware when the byte currently being received in the shift register is ready to be transferred into the spidr register while spif = 1 (see overrun condition (ovr) on page 128 ). an interrupt is gener ated if spie = 1 in spicr register. the ovr bit is cleared by software reading the spicsr register. 0: no overrun error 1: overrun error detected
st72321xx-auto serial peripheral interface (spi) doc id 13829 rev 1 133/243 14.8.3 data i/o register (spidr) the spidr register is used to transmit and receive data on the serial bus. in a master device, a write to this regi ster will initiate transmission/ reception of another byte. note: during the last clock cycle the spif bit is set, a copy of the received data byte in the shift register is moved to a buffer. when the user reads the serial peripheral data i/o register, the buffer is actually being read. while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read. 4modf mode fault flag this bit is set by hardware when the ss pin is pulled low in master mode (see master mode fault (modf) on page 128 ). an spi interrupt can be generated if spie = 1 in the spicsr register. this bit is cleared by a software sequence (an access to the spicr register while modf = 1 followed by a write to the spicr register). 0: no master mode fault detected 1: a fault in master mode has been detected 3 - reserved, must be kept cleared 2sod spi output disable this bit is set and cleared by software. when set, it disables the alternate function of the spi output (mosi in master mode / miso in slave mode). 0: spi output enabled (if spe = 1) 1: spi output disabled 1 ssm ss management this bit is set and cleared by software. when set, it disables the alternate function of the spi ss pin and uses the ssi bit value instead. see slave select management on page 123 . 0: hardware management (ss managed by external pin) 1: software management (internal ss signal controlled by ssi bit. external ss pin free for general-purpose i/o) 0 ssi ss internal mode this bit is set and cleared by software. it acts as a ?chip select? by controlling the level of the ss slave select signal when the ssm bit is set. 0: slave selected 1: slave deselected table 68. spicsr register description (continued) bit name function spidr reset value: undefined 76543210 d[7:0] rw
serial peripheral interface (spi) st72321xx-auto 134/243 doc id 13829 rev 1 warning: a write to the spidr register places data directly into the shift register for transmission. a read to the spidr register returns the value located in the buffer and not the content of the shift register (see figure 55 ). table 69. spi register map and reset values address (hex.) register label 76543210 0021h spidr reset value msb xxxxxxx lsb x 0022h spicr reset value spie 0 spe 0 spr2 0 mstr 0 cpol x cpha x spr1 x spr0 x 0023h spicsr reset value spif 0 wcol 0 ovr 0 modf 00 sod 0 ssm 0 ssi 0
st72321xx-auto serial communications interface (sci) doc id 13829 rev 1 135/243 15 serial communicati ons interface (sci) 15.1 introduction the serial communications interface (sci) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard nrz asynchronous serial data format. the sci offers a very wide range of baud rates using two baud rate generator systems. 15.2 main features full duplex, asynchronous communications nrz standard format (mark/space) dual baud rate generator systems independently programmable transmit and receive baud rates up to 500k baud programmable data word length (8 or 9 bits) receive buffer full, transmit buffer empty and end of transmission flags 2 receiver wake-up modes: ? address bit (msb) ? idle line muting function for multiprocessor configurations separate enable bits for transmitter and receiver 4 error detection flags: ? overrun error ? noise error ?frame error ? parity error 5 interrupt sources with flags: ? transmit data register empty ? transmission complete ? receive data register full ? idle line received ? overrun error detected parity control: ? transmits parity bit ? checks parity of received data byte reduced power consumption mode
serial communications interface (sci) st72321xx-auto 136/243 doc id 13829 rev 1 15.3 general description the interface is externally connected to another device by two pins (see figure 63 ): tdo: transmit data output. when the transmitter and the receiver are disabled, the output pin returns to its i/o port configuration. when the transmitter and/or the receiver are enabled and nothing is to be transmitted, the tdo pin is at high level. rdi: receive data input is the serial data input. oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. through these pins, serial data is transmitted and received as frames comprising: an idle line prior to transmission or reception a start bit a data word (8 or 9 bits) least significant bit first a stop bit indicating that the frame is complete this interface uses two types of baud rate generator: a conventional type for commonly-used baud rates an extended type with a prescaler offering a very wide range of baud rates even with non-standard osc illator frequencies
st72321xx-auto serial communications interface (sci) doc id 13829 rev 1 137/243 figure 62. sci block diagram wake up unit receiver control sr transmit control tdre tc rdrf idle or nf fe pe sci control interrupt cr1 r8 t8 scid m wake pce ps pie received data register (rdr) received shift register read transmit data register (tdr) transmit shift register write rdi tdo (data register) dr transmitter clock receiver clock receiver rate transmitter rate brr scp1 f cpu control control scp0 sct2 sct1 sct0 scr2 scr1scr0 /pr /16 conventional baud rate generator sbk rwu re te ilie rie tcie tie cr2
serial communications interface (sci) st72321xx-auto 138/243 doc id 13829 rev 1 15.4 functional description the block diagram of the serial control interface, is shown in figure 62 . it contains six dedicated registers: 2 control registers (scicr1 and scicr2) a status register (scisr) a baud rate register (scibrr) an extended prescaler receiver register (scierpr) an extended prescaler transmitter register (scietpr) refer to the register descriptions in section 15.7 for the definitions of each bit. 15.4.1 serial data format word length may be selected as being either 8 or 9 bits by programming the m bit in the scicr1 register (see figure 62 ). the tdo pin is in low state during the start bit. the tdo pin is in high state during the stop bit. an idle character is interpreted as an entire frame of ?1?s followed by the start bit of the next frame which contains data. a break character is interpreted on receiving ?0?s for some multiple of the frame period. at the end of the last break frame the transmitter inserts an extra ?1? bit to acknowledge the start bit. transmission and reception are driven by their own baud rate generator. figure 63. word length programming bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 start bit stop bit next start bit idle frame bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit start bit idle frame start bit 9-bit word length (m bit is set) 8-bit word length (m bit is reset) possible parity bit possible parity bit break frame start bit extra ?1? data frame break frame start bit extra ?1? data frame next data frame next data frame
st72321xx-auto serial communications interface (sci) doc id 13829 rev 1 139/243 15.4.2 transmitter the transmitter can send data words of either 8 or 9 bits depending on the m bit status. when the m bit is set, word length is 9 bits and the 9th bit (the msb) has to be stored in the t8 bit in the scicr1 register. character transmission during an sci transmission, data shifts out least significant bit first on the tdo pin. in this mode, the scidr register consists of a buffer (tdr) between the internal bus and the transmit shift register (see figure 62 ). procedure 1. select the m bit to define the word length. 2. select the desired baud rate using the scibrr and the scietpr registers. 3. set the te bit to assign the tdo pin to the alternate function and to send an idle frame as first transmission. 4. access the scisr register and write the data to send in the scidr register (this sequence clears the tdre bit). repeat this sequence for each data to be transmitted. clearing the tdre bit is always performed by the following software sequence: 1. an access to the scisr register 2. a write to the scidr register the tdre bit is set by hardware and it indicates: the tdr register is empty. the data transfer is beginning. the next data can be written in the scidr register without overwriting the previous data. this flag generates an interrupt if the tie bit is set and the i bit is cleared in the ccr register. when a transmission is taking place, a write instruction to the scidr register stores the data in the tdr register and which is copied in the shift register at the end of the current transmission. when no transmission is taking place, a write instruction to the scidr register places the data directly in the shift register, the data transmission starts, and the tdre bit is immediately set. when a frame transmission is complete (after the stop bit) the tc bit is set and an interrupt is generated if the tcie is set and the i bit is cleared in the ccr register. clearing the tc bit is performed by the following software sequence: 1. an access to the scisr register 2. a write to the scidr register note: the tdre and tc bits are cleared by the same software sequence. break characters setting the sbk bit loads the shi ft register with a br eak character. the break frame length depends on the m bit (see figure 63 ). as long as the sbk bit is set, the sci send br eak frames to the tdo pi n. after clearing this
serial communications interface (sci) st72321xx-auto 140/243 doc id 13829 rev 1 bit by software the sci insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. idle characters setting the te bit drives the sci to send an idle frame before the first data frame. clearing and then setting the te bit during a transmission sends an idle frame after the current word. note: resetting and setting the te bit causes the data in the tdr register to be lost. therefore the best time to toggle the te bit is when the tdre bit is set, that is, before writing the next byte in the scidr. 15.4.3 receiver the sci can receive data words of either 8 or 9 bits. when the m bit is set, word length is 9 bits and the msb is stored in the r8 bit in the scicr1 register. character reception during a sci reception, data shifts in least significant bit first through the rdi pin. in this mode, the scidr register consists or a buffer (rdr) between the internal bus and the received shift register (see figure 62 ). procedure 1. select the m bit to define the word length. 2. select the desired baud rate using the scibrr and the scierpr registers. 3. set the re bit, this enables the receiver which begins searching for a start bit. when a character is received: the rdrf bit is set. it indicates that the content of the shift register is transferred to the rdr. an interrupt is generated if the rie bit is set and the i bit is cleared in the ccr register. the error flags can be set if a frame error, noise or an overrun error has been detected during reception. clearing the rdrf bit is performed by th e following software sequence done by: 1. an access to the scisr register 2. a read to the scidr register. the rdrf bit must be cleared before the end of the reception of the next character to avoid an overrun error. break character when a break character is received, the sci handles it as a framing error. idle character when an idle frame is detected, there is the same procedure as a data received character plus an interrupt if the ilie bit is set and the i bit is cleared in the ccr register. overrun error an overrun error occurs when a character is received when rdrf has not been reset. data cannot be transferred from the shift register to the rdr register as long as the rdrf bit is not cleared.
st72321xx-auto serial communications interface (sci) doc id 13829 rev 1 141/243 when an overrun error occurs: the or bit is set. the rdr content is not lost. the shift register is overwritten. an interrupt is generated if the rie bit is set and the i bit is cleared in the ccr register. the or bit is reset by an access to the scisr register followed by a scidr register read operation. noise error oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. normal data bits are considered valid if three consecutive samples (8th, 9th, 10th) have the same bit value, otherwise the nf flag is set. in the case of start bit detection, the nf flag is set on the basis of an algorithm combining both valid edge detection and three samples (8th, 9th, 10th). therefore, to prevent the nf flag getting set during start bit reception, there should be a valid edge detection as well as three valid samples. when noise is detected in a frame: the nf flag is set at the rising edge of the rdrf bit. data is transferred from the shift register to the scidr register. no interrupt is generated. however this bit rises at the same time as the rdrf bit which itself generates an interrupt. the nf flag is reset by a scisr register read operation followed by a scidr register read operation. during reception, if a false start bit is detected (for example, 8th, 9th, 10th samples are 011, 101, 110), the frame is discarded and the receiving sequence is not started for this frame. there is no rdrf bit set for this frame and the nf flag is set internally (not accessible to the user). this nf flag is accessible along wit h the rdrf bit when a next valid frame is received. note: if the application start bit is not long enough to match the above requirements, then the nf flag may get set due to the short start bit. in this case, the nf flag may be ignored by the application software when the first valid byte is received. see also noise error causes on page 145 .
serial communications interface (sci) st72321xx-auto 142/243 doc id 13829 rev 1 figure 64. sci baud rate and extended prescaler block diagram framing error a framing error is detected when: the stop bit is not recognized on reception at the expected time, following either a de- synchronization or excessive noise. a break is received. when the framing error is detected: the fe bit is set by hardware. data is transferred from the shift register to the scidr register. no interrupt is generated. however this bit rises at the same time as the rdrf bit which itself generates an interrupt. the fe bit is reset by a scisr register read operation followed by a scidr register read operation. transmitter receiver scietpr scierpr extended prescaler rece iver rate control extended prescaler transmitter rate control extended prescaler clock clock receiver rate transmitter rate scibrr scp1 f cpu control control scp0 sct2 sct1 sct0 scr2 scr1 scr0 /pr /16 conventional baud rate generator extended receiver prescaler register extended transmitter prescaler register
st72321xx-auto serial communications interface (sci) doc id 13829 rev 1 143/243 conventional baud rate generation the baud rate for the receiver and transmitter (rx and tx) are set independently and calculated as follows: with: pr = 1, 3, 4 or 13 (see scp[1:0] bits) tr = 1, 2, 4, 8, 16, 32, 64,128 (see sct[2:0] bits) rr = 1, 2, 4, 8, 16, 32, 64,128 (see scr[2:0] bits) all these bits are in the scibrr register. example: if f cpu is 8 mhz (normal mode) and if pr = 13 and tr = rr = 1, the transmit and receive baud rates are 38400 baud. note: the baud rate registers must not be changed while the transmitter or the receiver is enabled. extended baud rate generation the extended prescaler option provides a very fine tuning of the baud rate, using a 255 value prescaler, whereas the conventional baud rate generator retains industry standard software compatibility. the extended baud rate generator block diagram is described in the figure 64 . the output clock rate sent to the transmitter or to the receiver is the output from the 16 divider divided by a factor ranging from 1 to 255 set in the scierpr or the scietpr register. note: the extended prescaler is activated by setting the scietpr or scierpr register to a value other than zero. the baud rates are calculated as follows: with: etpr = 1,..,255 (see scietpr register) erpr = 1,..,255 (see scierpr register) receiver muting and wake-up feature in multiprocessor configurations it is often desirable that only the intended message recipient should actively receive the full message contents, thus reducing redundant sci service overhead for all non-addressed receivers. the non-addressed devices may be placed in sleep mode by means of the muting function. setting the rwu bit by software puts the sci in sleep mode: all the reception status bits cannot be set. all the receive interrupts are inhibited. a muted receiver may be awakened by one of the following two ways: by idle line detection if the wake bit is reset by address mark detection if the wake bit is set tx = (16 * pr) * tr f cpu rx = (16 * pr) * rr f cpu tx = 16 * etpr * (pr * tr) f cpu rx = 16 * erpr * (pr * rr) f cpu
serial communications interface (sci) st72321xx-auto 144/243 doc id 13829 rev 1 a receiver wakes up by idle line detection when the receive line has recognized an idle frame. then the rwu bit is reset by hardware but the idle bit is not set. receiver wakes up by address mark detection wh en it received a ?1? as the most significant bit of a word, thus indicating that the message is an address. the reception of this particular word wakes up the receiver, resets the rwu bit and sets the rdrf bit, which allows the receiver to receive this word normally and to use it as an address word. caution: in mute mode, do not write to the scicr2 register. if the sci is in mute mode during the read operation (rwu = 1) and a address mark wake-up event occurs (rwu is reset) before the write operation, the rwu bit is set again by this write operation. consequently the address byte is lost and the sci is not woken up from mute mode. parity control parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the pce bit in the scicr1 register. depending on the frame length defined by the m bit, the possible sci frame formats are as listed in ta bl e 7 0 . legend: sb = start bit, stb = stop bit, pb = parity bit note: in case of wake-up by an address mark, the msb bit of the data is taken into account and not the parity bit even parity: the parity bit is calculated to obtain an even number of ?1?s inside the frame made of the 7 or 8 lsb bits (depending on whether m is equal to 0 or 1) and the parity bit. example: data = 00110101; 4 bits set => parity bit is 0 if even parity is selected (ps bit = 0). odd parity: the parity bit is calculated to obtain an odd number of ?1?s inside the frame made of the 7 or 8 lsb bits (depending on whether m is equal to 0 or 1) and the parity bit. example: data = 00110101; 4 bits set => parity bit is 1 if odd parity is selected (ps bit = 1). transmission mode: if the pce bit is set then the msb bit of the data written in the data register is not transmitted but is changed by the parity bit. reception mode: if the pce bit is set then the interface checks if the received data byte has an even number of ?1?s if even parity is selected (ps = 0) or an odd number of ?1?s if odd parity is selected (ps = 1). if the parity check fails, the pe flag is set in the scisr register and an interrupt is generated if pie is set in the scicr1 register. sci clock tolerance during reception, each bit is sampled 16 times. the majority of the 8th, 9th and 10th samples is considered as the bit value. for a valid bit detection, all the three samples should have the same value otherwise the noise flag (nf) is set. for example: if the 8th, 9th and 10th samples are 0, 1 and 1 respectively, then the bit value is ?1?, but the noise flag bit is set because the three samples values are not the same. table 70. frame formats m bit pce bit sci frame 0 0 | sb | 8 bit data | stb | 0 1 | sb | 7-bit data | pb | stb | 1 0 | sb | 9-bit data | stb | 1 1 | sb | 8-bit data pb | stb |
st72321xx-auto serial communications interface (sci) doc id 13829 rev 1 145/243 consequently, the bit length must be long enough so that the 8th, 9th and 10th samples have the desired bit value. this means the clock frequency should not vary more than 6/16 (37.5%) within one bit. the sampling clock is resynchronized at each start bit, so that when receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation must not exceed 3.75%. note: the internal samp ling clock of the microcontroller sa mples the pin value on every falling edge. therefore, the internal sampling clock and the time the application expects the sampling to take place may be out of sync. for example: if the baud rate is 15.625 kbaud (bit length is 64s), then the 8th, 9th and 10th samples are at 28s, 32s and 36s respectively (the first sample starting ideally at 0s). but if the falling edge of the internal clock occurs just before the pin value change s, the samples would then be out of sync by ~4us. this means the entire bit length must be at least 40s (36s for the 10th sample + 4s for synchronization with the internal sampling clock). clock deviation causes the causes which contribute to the total deviation are: ?d tra : deviation due to transmitter error (local oscillator error of the transmitter or the transmitter is transmitting at a different baud rate). ?d quant : error due to the baud rate quantization of the receiver. ?d rec : deviation of the local o scillator of the re ceiver: this deviation can occur during the reception of one complete sci message assuming that the deviation has been compensated at the beginning of the message. ?d tcl : deviation due to the transmission line (generally due to the transceivers) all the deviations of the system should be added and compared to the sci clock tolerance: d tra + d quant + d rec + d tcl < 3.75% noise error causes see also description of noise error in receiver on page 140 . start bit the noise flag (nf) is set during start bit reception if one of the following conditions occurs: 1. a valid falling edge is not de tected. a falling edge is consi dered to be valid if the 3 consecutive samples before the falling edge o ccurs are detected as ?1? and, after the falling edge occurs, during the sampling of the 16 samples, if one of the samples numbered 3, 5 or 7 is detected as a ?1?. 2. during sampling of the 16 samples, if one of the samples numbered 8, 9 or 10 is detected as a ?1?. therefore, a valid start bit must satisfy both the above conditions to prevent the noise flag getting set. data bits the noise flag (nf) is set during normal data bit reception if the following condition occurs: during the sampling of 16 samples, if all three samples numbered 8, 9 and10 are not the same. the majority of the 8th, 9th and 10th samples is considered as the bit value. therefore, a valid data bit must have samples 8, 9 and 10 at the same value to prevent the noise flag from getting set.
serial communications interface (sci) st72321xx-auto 146/243 doc id 13829 rev 1 figure 65. bit sampling in reception mode 15.5 low power modes 15.6 interrupts the sci interrupt events are connected to the same interrupt vector. these events generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). rdi line sample clock 1234567891011 12 13 14 15 16 sampled values one bit time 6/16 7/16 7/16 table 71. effect of low power modes on sci mode effect wait no effect on sci. sci interrupts cause the device to exit from wait mode. halt sci registers are frozen. in halt mode, the sci stops transmitting/ receiving until halt mode is exited. table 72. sci interrupt control/wake-up capability interrupt event event flag enable control bit exit from wait exit from halt transmit data register empty tdre tie yes no transmission complete tc tcie yes no received data ready to be read rdrf rie ye s n o overrun error detected or yes no
st72321xx-auto serial communications interface (sci) doc id 13829 rev 1 147/243 15.7 sci registers 15.7.1 status register (scisr) idle line detected idle ilie yes no parity error pe pie yes no table 72. sci interrupt control/wake-up capability interrupt event event flag enable control bit exit from wait exit from halt scisr reset value: 1100 0000 (c0h) 76543210 tdre tc rdrf idle or nf fe pe ro ro ro ro ro ro ro ro table 73. scisr register description bit name function 7tdre transmit data register empty this bit is set by hardware when the content of the tdr register has been transferred into the shift register. an interrupt is generated if the tie bit = 1 in the scicr2 register. it is cleared by a soft ware sequence (an access to the scisr register followed by a write to the scidr register). 0: data is not transferre d to the shift register 1: data is transferred to the shift register note: data is not transferred to the shift register unless the tdre bit is cleared. 6tc transmission complete this bit is set by hardware when transmission of a frame containing data is complete. an interrupt is ge nerated if tcie = 1 in the sc icr2 register. it is cleared by a software sequence (an access to the scisr register followed by a write to the scidr register). 0: transmission is not complete 1: transmission is complete note: tc is not set after the transmission of a preamble or a break. 5 rdrf received data ready flag this bit is set by hardware when the content of the rdr register has been transferred to the scidr register. an inte rrupt is generated if rie = 1 in the scicr2 register. it is cleared by a software se quence (an access to the scisr register followed by a read to the scidr register). 0: data is not received 1: received data is ready to be read
serial communications interface (sci) st72321xx-auto 148/243 doc id 13829 rev 1 4idle idle line detect this bit is set by hardware when an idle line is detected. an interrupt is generated if the ilie = 1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no idle line is detected 1: idle line is detected note: the idle bit is not set again until the rdrf bit has been set itself (that is, a new idle line occurs). 3or overrun error this bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the rdr register while rdrf = 1. an interrupt is generated if rie = 1 in the scicr2 regi ster. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no overrun error 1: overrun error is detected note: when this bit is set rdr register content is not lost but the shift register is overwritten. 2nf noise flag this bit is set by hardware when noise is detected on a received frame. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no noise is detected 1: noise is detected note: this bit does not generate interrupt as it appears at the same time as the rdrf bit which itself generates an interrupt. 1fe framing error this bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no framing error is detected 1: framing error or break character is detected note: this bit does not generate interrupt as it appears at the same time as the rdrf bit which itself generates an interrupt. if the word currently being transferred causes both frame error and overrun error, it will be transferred and only the or bit will be set. 0pe parity error this bit is set by hardware when a parity error occurs in receiver mode. it is cleared by a software sequence (a read to the status register followed by an access to the scidr data register). an interrupt is gene rated if pie = 1 in the scicr1 register. 0: no parity error 1: parity error table 73. scisr register description (continued) bit name function
st72321xx-auto serial communications interface (sci) doc id 13829 rev 1 149/243 15.7.2 control register 1 (scicr1) scicr1 reset value: x000 0000 (x0h) 76543210 r8 t8 scid m wake pce ps pie rw rw rw rw rw rw rw rw table 74. scicr1 register description bit name function 7r8 receive data bit 8 this bit is used to store the 9th bit of the received word when m = 1. 6t8 transmit data bit 8 this bit is used to store the 9th bit of the transmitted word when m = 1. 5scid disabled for low power consumption when this bit is set the sci prescalers and outputs are stopped and the end of the current byte transfer in order to reduce power consumption.this bit is set and cleared by software. 0: sci enabled 1: sci prescaler and outputs disabled 4m word length this bit determines the word length. it is set or cleared by software. 0: 1 start bit, 8 data bits, 1 stop bit 1: 1 start bit, 9 data bits, 1 stop bit note: the m bit must not be modified during a data transfer (both transmission and reception). 3 wake wake-up method this bit determines the sci wake-up meth od. it is set or cleared by software. 0: idle line 1: address mark 2pce parity control enable this bit selects the hardware parity control (generation and detection). when the parity control is enabled, the computed pari ty is inserted at the msb position (9th bit if m = 1; 8th bit if m = 0) and parity is checked on the received data. this bit is set and cleared by software. once it is set, pce is active after the current byte (in reception and in transmission). 0: parity control disabled 1: parity control enabled 1ps parity selection this bit selects the odd or even parity when the parity generation/detection is enabled (pce bit set). it is set and cleared by software. the parity is selected after the current byte. 0: even parity 1: odd parity
serial communications interface (sci) st72321xx-auto 150/243 doc id 13829 rev 1 15.7.3 control register 2 (scicr2) 0pie parity interrupt enable this bit enables the interrupt capability of the hardware parity control when a parity error is detected (pe bit set). it is set and cleared by software. 0: parity error interrupt disabled 1: parity error interrupt enabled table 74. scicr1 register description (continued) bit name function scicr2 reset value: 0000 0000 (00h) 76543210 tie tcie rie ilie te re rwu sbk rw rw rw rw rw rw rw rw table 75. scicr2 register description bit name function 7tie transmitter interrupt enable this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tdre = 1 in the scisr register. 6tcie transmission complete interrupt enable this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tc = 1 in the scisr register. 5rie receiver interrupt enable this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever or = 1 or rdrf = 1 in the scisr register. 4ilie idle line interrupt enable this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever idle = 1 in the scisr register. 3te transmitter enable this bit enables the transmitter. it is set and cleared by software. 0: transmitter is disabled 1: transmitter is enabled notes: during transmission, a ?0? pulse on the te bit (?0? followed by ?1?) sends a preamble (idle line) after the current word. when te is set there is a 1 bit-time delay before the transmission starts. caution : the tdo pin is free for general purpose i/o only when the te and re bits are both cleared (or if te is never set).
st72321xx-auto serial communications interface (sci) doc id 13829 rev 1 151/243 15.7.4 data register (scidr) this register contains the received or transmitted data character, depending on whether it is read from or written to. the data register performs a double function (r ead and write) since it is composed of two registers, one for transmission (t dr) and one for reception (rdr). the tdr register provides the parallel interface between the internal bus and the output shift register (see figure 62 ). the rdr register provides the parallel interface between the input shift register and the internal bus (see figure 62 ). 15.7.5 baud rate register (scibrr) 2re receiver enable this bit enables the receiver. it is set and cleared by software. 0: receiver is disabled 1: receiver is enabled and begins searching for a start bit 1rwu receiver wake-up this bit determines if the sci is in mute mode or not. it is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized. 0: receiver in active mode 1: receiver in mute mode note: before selecting mute mode (setting the rwu bit), the sci must receive some data first, otherwise it canno t function in mute mode with wake-up by idle line detection. 0 sbk send break this bit set is used to send break characters. it is set and cleared by software. 0: no break character is transmitted 1: break characters are transmitted note: if the sbk bit is set to ?1? and then to ?0?, the transmitter sends a break word at the end of the current word . table 75. scicr2 register description (continued) bit name function scidr reset value: undefined 76543210 dr[7:0] rw scibrr reset value: 0000 0000 (00h) 76543210 scp[1:0] sct[2:0] scr[2:0] rw rw rw
serial communications interface (sci) st72321xx-auto 152/243 doc id 13829 rev 1 15.7.6 extended receive prescaler division regi ster (scierpr) this register allows setting of the extended prescaler rate division factor for the receive circuit. table 76. scibrr register description bit name function 7:6 scp[1:0] first sci prescaler these 2 prescaling bits allow several standard clock division ranges. 00: pr prescaling factor = 1 01: pr prescaling factor = 3 10: pr prescaling factor = 4 11: pr prescaling factor = 13 5:3 sct[2:0] sci transmitter rate divisor these 3 bits, in conjunction with the scp1 and scp0 bits define the total division applied to the bus clock to yield the transmit rate clock in conventional baud rate generator mode. 000: tr dividing factor = 1 001: tr dividing factor = 2 010: tr dividing factor = 4 011: tr dividing factor = 8 100: tr dividing factor = 16 101: tr dividing factor = 32 110: tr dividing factor = 64 111: tr dividing factor = 128 2:0 scr[2:0] sci receiver rate divisor these 3 bits, in conjunction with the scp[1:0] bits define the total division applied to the bus clock to yield the receive rate clock in conventional baud rate generator mode. 000: rr dividing factor = 1 001: rr dividing factor = 2 010: rr dividing factor = 4 011: rr dividing factor = 8 100: rr dividing factor = 16 101: rr dividing factor = 32 110: rr dividing factor = 64 111: rr dividing factor = 128 scierpr reset value: 0000 0000 (00h) 76543210 erpr[7:0] rw
st72321xx-auto serial communications interface (sci) doc id 13829 rev 1 153/243 15.7.7 extended transm it prescaler divisi on register (scietpr) this register allows setting of the external prescaler rate division factor for the transmit circuit. table 77. scierpr register description bit name function 7:0 erpr[7:0] 8-bit extended receive prescaler register the extended baud rate generator is activa ted when a value different from 00h is stored in this register. therefore the cl ock frequency issued from the 16 divider (see figure 64 ) is divided by the binary factor set in the scierpr register (in the range 1 to 255). the extended baud rate generator is not used after a reset. scietpr reset value: 0000 0000 (00h) 76543210 etpr[7:0] rw table 78. scietpr register description bit name function 7:0 etpr[7:0] 8-bit extended transmit prescaler register the extended baud rate generator is activa ted when a value different from 00h is stored in this register. therefore the cl ock frequency issued from the 16 divider (see figure 64 ) is divided by the binary factor set in the scietpr register (in the range 1 to 255). the extended baud rate generator is not used after a reset. table 79. baud rate selection symbol parameter conditions standard baud rate unit f cpu accuracy versus standard prescaler f tx f rx communication frequency 8mhz ~0.16% conventional mode tr (or rr) = 128, pr = 13 tr (or rr) = 32, pr = 13 tr (or rr) = 16, pr = 13 tr (or rr) = 8, pr = 13 tr (or rr) = 4, pr = 13 tr (or rr) = 16, pr = 3 tr (or rr) = 2, pr = 13 tr (or rr) = 1, pr = 13 300 1200 2400 4800 9600 10400 19200 38400 ~300.48 ~1201.92 ~2403.84 ~4807.69 ~9615.38 ~10416.67 ~19230.77 ~38461.54 hz ~0.79% extended mode etpr (or erpr) = 35, tr (or rr) = 1, pr = 1 14400 ~14285.71
serial communications interface (sci) st72321xx-auto 154/243 doc id 13829 rev 1 table 80. sci register map and reset values address (hex.)register label76543210 0050h scisr reset value tdre 1 tc 1 rdrf 0 idle 0 or 0 nf 0 fe 0 pe 0 0051h scidr reset value msb xxxxxxx lsb x 0052h scibrr reset value scp1 0 scp0 0 sct2 0 sct1 0 sct0 0 scr2 0 scr1 0 scr0 0 0053h scicr1 reset value r8 x t8 0 scid 0 m 0 wake 0 pce 0 ps 0 pie 0 0054h scicr2 reset value tie 0 tcie 0 rie 0 ilie 0 te 0 re 0 rwu 0 sbk 0 0055h scierpr reset value msb 0000000 lsb 0 0057h scipetpr reset value msb 0000000 lsb 0
st72321xx-auto i2c bus interface (i2c) doc id 13829 rev 1 155/243 16 i 2 c bus interface (i2c) 16.1 introduction the i 2 c bus interface serves as an interface between the microcontroller and the serial i 2 c bus. it provides both multimaster and slave functions, and controls all i 2 c bus-specific sequencing, protocol, arbitration and timing. it supports fast i 2 c mode (400 khz). 16.2 main features parallel-bus/i 2 c protocol converter multimaster capability 7-bit/10-bit addressing smbus v1.1 compliant transmitter/receiver flag end-of-byte transmission flag transfer problem detection 16.2.1 i 2 c master features clock generation i 2 c bus busy flag arbitration lost flag end of byte transmission flag transmitter/receiver flag start bit detection flag start and stop generation 16.2.2 i 2 c slave features stop bit detection i 2 c bus busy flag detection of misplaced start or stop condition programmable i 2 c address detection transfer problem detection end-of-byte transmission flag transmitter/receiver flag
i2c bus interface (i2c) st72321xx-auto 156/243 doc id 13829 rev 1 16.3 general description in addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa, using either an interrupt or polled handshake. the interrupts are enabled or disabled by software. the interface is connected to the i 2 c bus by a data pin (sdai) and by a clock pin (scli). it can be connected both with a standard i 2 c bus and a fast i 2 c bus. this selection is made by software. 16.3.1 mode selection the interface can operate in the four following modes: slave transmitter/receiver master transmitter/receiver by default, it operates in slave mode. the interface automatically switches from slave to master after it generates a start condition and from master to slave in case of arbitration loss or a stop generation, allowing then multimaster capability. 16.3.2 communication flow in master mode, it initiates a data transfer and generates the clock signal. a serial data transfer always begins with a start condition and ends with a stop condition. both start and stop conditions are generated in master mode by software. in slave mode, the interface is capable of reco gnizing its own address (7- or 10-bit), and the general call address. the general call address detection may be enabled or disabled by software. data and addresses are transferred as 8-bit bytes, msb first. the first byte(s) following the start condition contain the address (one in 7-bit mode, two in 10-bit mode). the address is always transmitted in master mode. a 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. refer to figure 66 . figure 66. i 2 c bus protocol acknowledge may be enabled and disabled by software. the i 2 c interface address and/or general call address can be selected by software. the speed of the i 2 c interface may be selected between standard (up to 100 khz) and fast i 2 c (up to 400 khz). scl sda 12 8 9 msb ack stop start condition condition vr02119b
st72321xx-auto i2c bus interface (i2c) doc id 13829 rev 1 157/243 16.3.3 sda/scl line control transmitter mode the interface holds the clock line low before transmission to wait for the microcontroller to write the byte in the data register. receiver mode the interface holds the clock line low after reception to wait fo r the microcontroller to read the byte in the data register. the scl frequency (f scl ) is controlled by a programmable clock divider which depends on the i 2 c bus mode. when the i 2 c cell is enabled, the sda and scl ports must be configured as floating inputs. in this case, the value of the external pull-up resistor used depends on the application. when the i 2 c cell is disabled, the sda and scl ports revert to being standard i/o port pins. figure 67. i 2 c interface block diagram data register (dr) data shift register comparator own address register 1 (oar1) clock control register (ccr) status register 1 (sr1) control register (cr) control logic status register 2 (sr2) interrupt clock control data control scl or scli sda or sdai own address register 2 (oar2)
i2c bus interface (i2c) st72321xx-auto 158/243 doc id 13829 rev 1 16.4 functional description refer to the cr, sr1 and sr2 registers in section 16.7 for the bit definitions. by default the i 2 c interface operates in slave mode (m/sl bit is cleared) except when it initiates a transmit or receive sequence. first the interface frequency must be configured using the fri bits in the oar2 register. 16.4.1 slave mode as soon as a start condition is detected, the address is received from the sda line and sent to the shift register; then it is compared with the address of the interface or the general call address (if selected by software). note: in 10-bit addressing mode, the comparison includes the header sequence (11110xx0) and the two most significant bits of the address. header matched (10-bit mode only): the interface generates an acknowledge pulse if the ack bit is set. address not matched : the interface ignores it and waits for another start condition. address matched : the interface generates in sequence: an acknowledge pulse if the ack bit is set evf and adsl bits are set with an interrupt if the ite bit is set. then the interface waits for a read of the sr1 register, holding the scl line low (see figure 68: transfer sequencing ev1). next, in 7-bit mode read the dr register to determine from the least significant bit (data direction bit) if the slave must enter receiver or transmitter mode. in 10-bit mode, after receiving the address sequence the slave is always in receive mode. it will enter transmit mode on rece iving a repeated start condit ion followed by the header sequence with matching address bits and the least significant bit set (11110xx1). slave receiver following the address reception and after the sr1 register has been read, the slave receives bytes from the sda line into the dr register via the internal shift register. after each byte the interface generates in sequence: an acknowledge pulse if the ack bit is set evf and btf bits are set with an interrupt if the ite bit is set. then the interface waits for a read of the sr1 register followed by a read of the dr register, holding the scl line low (see figure 68: transfer sequencing ev2). slave transmitter following the address reception and after sr1 register has been read, the slave sends bytes from the dr register to the sda line via the internal shift register. the slave waits for a read of the sr1 register followed by a write in the dr register, holding the scl line low (see figure 68: transfer sequencing ev3). when the acknowledge pulse is received: the evf and btf bits are set by hardware with an interrupt if the ite bit is set.
st72321xx-auto i2c bus interface (i2c) doc id 13829 rev 1 159/243 closing slave communication after the last data byte is transferred, a stop condition is generated by the master. the interface detects this condition and sets: evf and stopf bits with an interrupt if the ite bit is set. then the interface waits for a read of the sr2 register (see figure 68: transfer sequencing ev4). error cases berr : detection of a stop or a start condition during a byte transfer. in this case, the evf and the berr bits are set with an interrupt if the ite bit is set. if it is a stop then the interface discards the data, released the lines and waits for another start condition. if it is a start then the interface discards the data and waits for the next slave address on the bus. af : detection of a non-acknowledge bit. in this case, the evf and af bits are set with an interrupt if the ite bit is set. the af bit is cleared by reading the i2csr2 register. however, if read before the completion of the transmission, the af flag will be set again, thus possibly generating a new interrupt. software must ensure either that the scl line is back at 0 before reading the sr2 register, or be able to correctly handle a second interrupt during the 9th pulse of a transmitted byte. note: in case of errors, the scl line is not held low; however, the sda line can remain low if the last bits transmitted are all 0. while af = 1, the scl line may be held low due to sb or btf flags that are set at the same time. it is then necessary to release both lines by software. how to release the sda / scl lines set and subsequently clear the stop bit while btf is set. the sda/scl lines are released after the transfer of the current byte. smbus compatibility the st7 i 2 c is compatible with the smbus v1.1 protocol. it supports all smbus addressing modes, smbus bus protocols and crc-8 packet error checking. refer to smbus slave driver for st7 i 2 c peripheral (an1713). 16.4.2 master mode to switch from default slave mode to master mode a start condition generation is needed. start condition setting the start bit while the busy bit is cleared causes the interface to switch to master mode (m/sl bit set) and generates a start condition. once the start condition is sent: the evf and sb bits are set by hardware with an interrupt if the ite bit is set. then the master waits for a read of the sr1 register followed by a write in the dr register with the slave address, holding the scl line low (see figure 68: transfer sequencing ev5).
i2c bus interface (i2c) st72321xx-auto 160/243 doc id 13829 rev 1 slave address transmission then the slave address is sent to the sda line via the internal shift register. in 7-bit addressing mode, one address byte is sent. in 10-bit addressing mode, sending the first byte including the header sequence causes the following event: ? the evf bit is set by hardware with interrupt generation if the ite bit is set. then the master waits for a read of the sr1 register followed by a write in the dr register, holding the scl line low (see figure 68: transfer sequencing ev9). then the second address byte is sent by the interface. after completion of this transfer (and acknowledge from the slave if the ack bit is set): the evf bit is set by hardware with interrupt generation if the ite bit is set. then the master waits for a read of the sr1 register followed by a write in the cr register (for example set pe bit), holding the scl line low (see figure 68: transfer sequencing ev6). next, the master must enter receiver or transmitter mode. note: in 10-bit addressing mode, to switch the master to receiver mode, software must generate a repeated start condition and resend the header sequence with the least significant bit set (11110xx1). master receiver following the address transmission and after sr1 and cr registers have been accessed, the master receives bytes from the sda line into the dr register via the internal shift register. after each byte the interface generates in sequence: acknowledge pulse if the ack bit is set evf and btf bits are set by hardware with an interrupt if the ite bit is set. then the interface waits for a read of the sr1 register followed by a read of the dr register, holding the scl line low (see figure 68: transfer sequencing ev7). to close the communication: before reading the last byte from the dr register, set the stop bit to generate the stop condition. the interface goes automatically back to slave mode (m/sl bit cleared). note: in order to generate the non-acknowledge pulse after the last received data byte, the ack bit must be cleared just before reading the second last data byte. master transmitter following the address transmission and after sr1 register has been read, the master sends bytes from the dr register to the sda line via the internal shift register. the master waits for a read of the sr1 register followed by a write in the dr register, holding the scl line low (see figure 68: transfer sequencing ev8). when the acknowledge bit is received, the interface sets: evf and btf bits with an interrupt if the ite bit is set. to close the communication: after writing the last byte to the dr register, set the stop bit to generate the stop condition. the interface goes automatically back to slave mode (m/sl bit cleared).
st72321xx-auto i2c bus interface (i2c) doc id 13829 rev 1 161/243 error cases berr : detection of a stop or a start condition during a byte transfer. in this case, the evf and berr bits are set by hardware with an interrup t if ite is set. note that berr will not be set if an error is detected during the first or second pulse of each 9-bit transaction: ? single master mode if a start or stop is issued during the first or second pulse of a 9-bit transaction, the berr flag will not be set and transfer will continue however the busy flag will be reset. to work around this, slave devices should issue a nack when they receive a misplaced start or stop. the reception of a nack or busy by the master in the middle of communication makes it possible to re-initiate transmission. ? multimaster mode normally the berr bit would be set whenever unauthorized transmission takes place while transfer is already in progress. however, an issue will arise if an external master generates an unauthorized start or stop while the i 2 c master is on the first or second pulse of a 9-bit transaction. it is possible to work around this by polling the busy bit during i 2 c master mode transmission. the resetting of the busy bit can then be handled in a similar manner as the berr flag being set. af : detection of a non-acknowledge bit. in this case, the evf and af bits are set by hardware with an interrupt if the ite bit is set. to resume, set the start or stop bit. the af bit is cleared by reading the i2csr2 register. however, if read before the completion of the transmission, the af flag will be set again, thus possibly generating a new interrupt. software must ensure either that the scl line is back at 0 before reading the sr2 register, or be able to correctly handle a second interrupt during the 9th pulse of a transmitted byte. arlo: detection of an arbitration lost condition. in this case the arlo bit is set by hardware (with an interrupt if the ite bit is set and the interface goes automatically back to slave mode (the m/sl bit is cleared). note: in all these cases, the scl line is not held low; however, the sda line can remain low due to possible ?0? bits transmitted last. it is then necessary to release both lines by software.
i2c bus interface (i2c) st72321xx-auto 162/243 doc id 13829 rev 1 figure 68. transfer sequencing 7-bit slave receiver: 7-bit slave transmitter: 7-bit master receiver: 7-bit master transmitter: 10-bit slave receiver: 10-bit slave transmitter: 10-bit master transmitter: 10-bit master receiver: s address a data1 a data2 a ..... datan a p ev1 ev2 ev2 ev2 ev4 s address a data1 a data2 a ..... datan na p ev1 ev3 ev3 ev3 ev3-1 ev4 s address a data1 a data2 a ..... datan na p ev5 ev6 ev7 ev7 ev7 s address a data1 a data2 a ..... datan a p ev5 ev6 ev8 ev8 ev8 ev8 s header a address a data1 a ..... datan a p ev1 ev2 ev2 ev4 s r header a data1 a .... . datan a p ev1 ev3 ev3 ev3-1 ev4 s header a address a data1 a ..... datan a p ev5 ev9 ev6 ev8 ev8 ev8 s r header a data1 a ..... datan a p ev5 ev6 ev7 ev7 legend: s = start, sr = repeated start, p = stop, a = acknowledge, na = non-acknowledge, evx = event (with interrupt if ite = 1) ev1: evf = 1, adsl = 1, cleared by reading sr1 register. ev2: evf = 1, btf = 1, cleared by reading sr1 register followed by reading dr register. ev3: evf = 1, btf = 1, cleared by reading sr1 register followed by writing dr register. ev3-1: evf = 1, af = 1, btf = 1; af is cleared by reading sr1 register . btf is cleared by releasing the lines (stop = 1, stop = 0) or by writing dr register (dr = ffh). note: if lines are released by stop = 1, stop = 0, the subsequent ev4 is not seen. ev4: evf = 1, stopf = 1, cleared by reading sr2 register. ev5: evf = 1, sb = 1, cleared by reading sr1 register followed by writing dr register. ev6: evf = 1, cleared by reading sr1 register followed by writing cr register (for example pe = 1). ev7: evf = 1, btf = 1, cleared by reading sr1 register followed by reading dr register. ev8: evf = 1, btf = 1, cleared by reading sr1 register followed by writing dr register. ev9: evf = 1, add10 = 1, cleared by reading sr1 register followed by writing dr register.
st72321xx-auto i2c bus interface (i2c) doc id 13829 rev 1 163/243 16.5 low power modes 16.6 interrupts figure 69. interrupt control logic diagram note: the i 2 c interrupt events are connected to the same interrupt vector (see interrupts chapter). they generate an interrupt if the corresponding enable control bit is set and the i-bit in the cc register is reset (rim instruction). table 81. effect of low power modes on i 2 c mode effect wait no effect on i 2 c interface. i 2 c interrupts cause the device to exit from wait mode. halt i 2 c registers are frozen. in halt mode, the i 2 c interface is inactive and does not acknowledge data on the bus. the i 2 c interface resumes operation when the mcu is woken up by an interrupt with ?exit from halt mode? capability. table 82. i 2 c interrupt control/wake-up capability interrupt event event flag enable control bit exit from wait exit from halt 10-bit address sent event (master mode) add10 ite yes no end of byte transfer event btf address matched event (slave mode) adsel start bit generation event (master mode) sb acknowledge failure event af stop detection event (slave mode) stopf arbitration lost event (multimaster configuration) arlo bus error event berr btf adsl sb af stopf arlo berr evf interrupt ite * * evf can also be set by ev6 or an error from the sr2 register. add10
i2c bus interface (i2c) st72321xx-auto 164/243 doc id 13829 rev 1 16.7 register description 16.7.1 i 2 c control register (cr) cr reset value: 0000 0000 (00h) 76543210 reserved pe engc start ack stop ite - rwrwrwrwrwrw table 83. cr register description bit name function 7:6 - reserved. forced to 0 by hardware. 5pe peripheral enable this bit is set and cleared by software. 0: peripheral disabled 1: master/slave capability notes: - when pe = 0, all the bits of the cr regist er and the sr register except the stop bit are reset. all outputs are released while pe = 0 - when pe = 1, the corresponding i/o pins are selected by hardware as alternate functions. to enable the i 2 c interface, write the cr register twice with pe = 1 as the first write only activates the interface (only pe is set). 4engc enable general call this bit is set and cleared by software. it is also cleared by hardware when the interface is disabled (pe = 0). the 00h general call address is acknowledged (01h ignored). 0: general call disabled 1: general call enabled note: in accordance with the i2c standard, when gcal addressing is enabled, an i2c slave can only receive data. it will not transmit data to the master. 3start generation of a start condition this bit is set and cleared by software. it is also cleared by hardware when the interface is disabled (pe = 0) or when the start condition is sent (with interrupt generation if ite = 1). in master mode 0: no start generation 1: repeated start generation in slave mode 0: no start generation 1: start generation when the bus is free 2ack acknowledge enable this bit is set and cleared by software. it is also cleared by hardware when the interface is disabled (pe = 0). 0: no acknowledge returned 1: acknowledge returned after an address byte or a data byte is received
st72321xx-auto i2c bus interface (i2c) doc id 13829 rev 1 165/243 16.7.2 i 2 c status register 1 (sr1) 1stop generation of a stop condition this bit is set and cleared by software. it is also cleared by hardware in master mode. note: this bit is not cleared when the interface is disabled (pe = 0). in master mode 0: no stop generation 1: stop generation after the current byte tr ansfer or after the current start condition is sent. the stop bit is cleared by har dware when the stop condition is sent. in slave mode 0: no stop generation 1: release the scl and sda lines after the current byte transfer (btf = 1). in this mode the stop bit has to be cleared by software. 0ite interrupt enable this bit is set and cleared by software and cleared by hardware when the interface is disabled (pe = 0). 0: interrupts disabled 1: interrupts enabled refer to figure 69 and ta b l e 8 2 for the relationship bet ween the events and the interrupt. scl is held low when the add10, sb, btf or adsl flags or an ev6 event (see figure 68 ) is detected. table 83. cr register description (continued) bit name function sr1 reset value: 0000 0000 (00h) 76543210 evf add10 tra busy btf adsl m/sl sb ro ro ro ro ro ro ro ro table 84. sr1 register description bit name function 7evf event flag this bit is set by hardware as soon as an event occurs. it is cleared by software reading sr2 register in case of error event or as described in figure 68 . it is also cleared by hardware when the interface is disabled (pe = 0). 0: no event 1: one of the following events has occurred: - btf = 1 (byte received or transmitted) - adsl = 1 (address matched in slave mode while ack = 1) - sb = 1 (start condition generated in master mode) - af = 1 (no acknowledge received after byte transmission) - stopf = 1 (stop condition detected in slave mode) - arlo = 1 (arbitration lost in master mode) - berr = 1 (bus error, misplaced start or stop condition detected) - add10 = 1 (master has sent header byte) - address byte successfully transmitted in master mode
i2c bus interface (i2c) st72321xx-auto 166/243 doc id 13829 rev 1 6 add10 10-bit addressing in master mode this bit is set by hardware when the master has sent the first byte in 10-bit address mode. it is cleared by software reading sr2 register followed by a write in the dr register of the second address byte. it is also cleared by hardware when the peripheral is disabled (pe = 0). 0: no add10 event occurred. 1: master has sent first address byte (header) 5tra transmitter/receiver when btf is set, tra = 1 if a data byte has been transmitted. it is cleared automatically when btf is cleared. it is also cleared by hardware after detection of stop condition (stopf = 1), loss of bus arbitration (arlo = 1) or when the interface is disabled (pe = 0). 0: data byte received (if btf = 1) 1: data byte transmitted 4busy bus busy this bit is set by hardware on detection of a start condition and cleared by hardware on detection of a stop condition. it indicates a communication in progress on the bus. the busy flag of the i2csr1 register is cleared if a bus error occurs. 0: no communication on the bus 1: communication ongoing on the bus note: the busy flag is not updated when t he interface is disabled (pe = 0). this can have consequences when operating in multimaster mode; that is, a second active i 2 c master commencing a transfer with an unset busy bit can cause a conflict resulting in lost data. a software workaround consists of checking that the i 2 c is not busy before enabling the i 2 c multimaster cell. 3btf byte transfer finished this bit is set by hardware as soon as a by te is correctly received or transmitted with interrupt generation if ite = 1. it is cl eared by software reading sr1 register followed by a read or write of dr register. it is also cleared by hardware when the interface is disabled (pe = 0). following a byte transmission, this bit is set after reception of the acknowledge clock pulse. in case an address byte is sent, this bit is set only after the ev6 event (see figure 68 ). btf is cleared by reading sr1 regist er followed by writing the next byte in dr register. following a byte reception, this bit is set after transmission of the acknowledge clock pulse if ack = 1. btf is cleared by reading sr1 register followed by reading the byte from dr register. the scl line is held low while btf = 1. 0: byte transfer not done 1: byte transfer succeeded 2adsl address matched (slave mode) this bit is set by hardware as soon as the received slave address matched with the oar register content or a general call is recognized. an interrupt is generated if ite = 1. it is cleared by software readi ng sr1 register or by hardware when the interface is disabled (pe = 0). the scl line is held low while adsl = 1. 0: address mismatched or not received 1: received address matched table 84. sr1 register description (continued) bit name function
st72321xx-auto i2c bus interface (i2c) doc id 13829 rev 1 167/243 16.7.3 i 2 c status register 2 (sr2) 1m/sl master/slave this bit is set by hardware as soon as the interface is in master mode (writing start = 1). it is cleared by hardware after detecting a stop condition on the bus or a loss of arbitration (arlo = 1). it is also cleared when the interface is disabled (pe = 0). 0: slave mode 1: master mode 0sb start bit (master mode) this bit is set by hardware as soon as the start condition is generated (following a write start = 1). an interrupt is generated if ite = 1. it is cleared by software reading sr1 register followed by writing the address byte in dr register. it is also cleared by hardware when the interface is disabled (pe = 0). 0: no start condition 1: start condition generated table 84. sr1 register description (continued) bit name function sr2 reset value: 0000 0000 (00h) 76543210 reserved af stopf arlo berr gcal - rororororo table 85. sr2 register description bit name function 7:5 - reserved. forced to 0 by hardware. 4af acknowledge failure this bit is set by hardware when no acknowledge is returned. an interrupt is generated if ite = 1. it is cleared by soft ware reading sr2 register or by hardware when the interface is disabled (pe = 0). the scl line is not held low while af = 1 but by other flags (sb or btf) that are set at the same time. 0: no acknowledge failure 1: acknowledge failure note: when an af event occurs, the scl line is not held low; however, the sda line can remain low if the last bits transmitted are all 0. it is then necessary to release both lines by software. 3stopf stop detection (slave mode) this bit is set by hardware when a stop condition is detected on the bus after an acknowledge (if ack = 1). an interrupt is generated if ite = 1. it is cleared by software reading sr2 register or by hardware when the interface is disabled (pe = 0). the scl line is not held low while stopf = 1. 0: no stop condition detected 1: stop condition detected
i2c bus interface (i2c) st72321xx-auto 168/243 doc id 13829 rev 1 16.7.4 i 2 c clock control register (ccr) 2arlo arbitration lost this bit is set by hardware when the inte rface loses the arbitration of the bus to another master. an interrupt is generated if ite = 1. it is cleared by software reading sr2 register or by hardware when the interface is disabled (pe = 0). after an arlo event the interface swit ches back automatically to slave mode (m/sl = 0). the scl line is not held low while arlo = 1. 0: no arbitration lost detected 1: arbitration lost detected note: in a multimaster environment, when the interface is configured in master receive mode it does not perform arbitration during the reception of the acknowledge bit. mishandling of the arlo bit from the i2csr2 register may occur when a second master simultaneously requests the same data from the same slave and the i 2 c master does not acknowledge the dat a. the arlo bit is then left at 0 instead of being set. 1berr bus error this bit is set by hardware when the in terface detects a misp laced start or stop condition. an interrupt is generated if ite = 1. it is cleared by software reading sr2 register or by hardware when the interface is disabled (pe = 0). the scl line is not held low while berr = 1. 0: no misplaced start or stop condition 1: misplaced start or stop condition note: if a bus error occurs, a stop or a repeated start condition should be generated by the master to re-synchroni ze communication, get the transmission acknowledged and the bus released for further communication. 0gcal general call (slave mode) this bit is set by hardware when a general call address is detected on the bus while engc = 1. it is cleared by hardware detecting a stop condition (stopf = 1) or when the interface is disabled (pe = 0). 0: no general call address detected on bus 1: general call address detected on bus table 85. sr2 register description (continued) bit name function ccr reset value: 0000 0000 (00h) 76543210 fm/sm cc[6:0] rw rw table 86. ccr register description bit name function 7fm/sm fast/standard i 2 c mode this bit is set and cleared by software. it is not cleared when the interface is disabled (pe = 0). 0: standard i 2 c mode 1: fast i 2 c mode
st72321xx-auto i2c bus interface (i2c) doc id 13829 rev 1 169/243 16.7.5 i 2 c data register (dr) 16.7.6 i 2 c own address register (oar1) 6:0 cc[6:0] 7-bit clock divider these bits select the speed of the bus (f scl ) depending on the i 2 c mode. they are not cleared when the interface is disabled (pe = 0). refer to section 19: electrical characteristics for the table of values. note: the programmed f scl assumes no load on scl and sda lines. table 86. ccr register description (continued) bit name function dr reset value: 0000 0000 (00h) 76543210 d[7:0] rw table 87. dr register description bit name function 7:0 d[7:0] 8-bit data register these bits contain the byte to be received or transmitted on the bus. transmitter mode: byte transmission start automatically when the software writes in the dr register. receiver mode: the first data byte is received automatically in the dr register using the least significant bit of the address. then, the following data bytes are received one by one after reading the dr register. oar1 reset value: 0000 0000 (00h) 76543210 add7 add6 add5 add4 add3 add2 add1 add0 rw rw rw rw rw rw rw rw
i2c bus interface (i2c) st72321xx-auto 170/243 doc id 13829 rev 1 16.7.7 i 2 c own address register (oar2) table 88. oar1 register description bit name function 7-bit addressing mode 10- bit addressing mode 7:1 add[7:1] interface address these bits define the i 2 c bus address of the interface. they are not cleared when the interface is disabled (pe = 0). not applicable 0 add0 address direction bit this bit is ?don?t care?, the interface acknowledges either 0 or 1. it is not cleared when the interface is disabled (pe = 0). address 01h is always ignored. 7:0 add[7:0] not applicable interface address these are the least significant bits of the i 2 c bus address of the interface. they are not cleared when the interface is disabled (pe = 0). oar2 reset value: 0100 0000 (40h) 76543210 fr[1:0] reserved add[9:8] reserved rw - rw - table 89. oar2 register description bit name function 7:6 fr[1:0] frequency bits these bits are set by software only when the interface is disabled (pe = 0). to configure the interface to i 2 c specified delays, select the value corresponding to the cpu frequency f cpu . 00: f cpu < 6 mhz 01: f cpu = 6 to 8 mhz 5:3 - reserved 2:1 add[9:8] interface address these are the most sign ificant bits of the i 2 c bus address of the interface (10-bit mode only). they are not cleared when the interface is disabled (pe = 0). 0-reserved
st72321xx-auto i2c bus interface (i2c) doc id 13829 rev 1 171/243 table 90. i 2 c register map and reset values address (hex.) register label 76543210 0018h i2ccr reset value 0 0 pe 0 engc 0 start 0 ack 0 stop 0 ite 0 0019h i2csr1 reset value evf 0 add10 0 tra 0 busy 0 btf 0 adsl 0 m/sl 0 sb 0 001ah i2csr2 reset value 0 0 0 af 0 stopf 0 arlo 0 berr 0 gcal 0 001bh i2cccr reset value fm/sm 0 cc6 0 cc5 0 cc4 0 cc3 0 cc2 0 cc1 0 cc0 0 001ch i2coar1 reset value add7 0 add6 0 add5 0 add4 0 add3 0 add2 0 add1 0 add0 0 001dh i2coar2 reset value fr1 0 fr0 1000 add9 0 add8 00 001eh i2cdr reset value msb 0000000 lsb 0
10-bit a/d converter (adc) st72321xx-auto 172/243 doc id 13829 rev 1 17 10-bit a/d converter (adc) 17.1 introduction the on-chip analog to digital converter (adc) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. this peripheral has up to 16 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 16 different sources. the result of the conversion is stored in a 10-bit data register. the a/d converter is controlled through a control/status register. 17.2 main features 10-bit conversion up to 16 channels with multiplexed input linear successive approximation data register (dr) whic h contains the results conversion complete status flag on/off bit (to reduce consumption) the block diagram is shown in figure 70 . figure 70. adc block diagram ch2 ch1 eoc speed adon 0 ch0 adccsr ain0 ain1 analog to digital converter ainx analog mux d4 d3 d5 d9 d8 d7 d6 d2 adcdrh 4 div 4 f adc f cpu d1 d0 adcdrl 0 1 00 0000 ch3 div 2
st72321xx-auto 10-bit a/d converter (adc) doc id 13829 rev 1 173/243 17.3 functional description the conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not. if the input voltage (v ain ) is greater than v aref (high-level voltage reference) then the conversion result is ffh in the adcdrh register and 03h in the adcdrl register (without overflow indication). if the input voltage (v ain ) is lower than v ssa (low-level voltage reference) then the conversion result in the adcdrh an d adcdrl registers is 00 00h. the a/d converter is linear and the digital result of the conv ersion is stored in the adcdrh and adcdrl registers. the accuracy of the conversion is described in section 19: electrical characteristics . r ain is the maximum recommended impedance for an analog input signal. if the impedance is too high, this will result in a loss of accuracy due to leakage and samp ling not being completed in the allotted time. 17.3.1 a/d converter configuration the analog input ports must be configured as input, no pull-up, no interrupt. refer to the chapter 9: i/o ports . using these pins as analog inputs does not affect the ability of the port to be read as a logic input. in the adccsr register: select the cs[3:0] bits to assign the analog channel to convert. 17.3.2 starting the conversion in the adccsr register: set the adon bit to enable the a/d converter and to start the conversion. from this time on, the adc performs a continuous conversion of the selected channel. when a conversion is complete: the eoc bit is set by hardware. the result is in the adcdr registers. a read to the adcdrh or a write to any bit of the adccsr register resets the eoc bit. to read the 10 bits, perform the following steps: 1. poll the eoc bit. 2. read the adcdrl register. 3. read the adcdrh register. th is clears eoc automatically. note: the data is not latched, so both the low and the high data register must be read before the next conversion is complete, so it is recommended to disable interrupts while reading the conversion result. to read only 8 bits, perform the following steps: 1. poll the eoc bit. 2. read the adcdrh register. th is clears eoc automatically.
10-bit a/d converter (adc) st72321xx-auto 174/243 doc id 13829 rev 1 17.3.3 changing the conversion channel the application can change channels during conversion. when software modifies the ch[3:0] bits in the adccsr register, the cu rrent conversion is stopped, the eoc bit is cleared, and the a/d converter starts converting the newly selected channel. 17.4 low power modes note: the a/d converter may be disabled by resetting the adon bit. this feature allows reduced power consumption when no conversion is needed and between single shot conversions. 17.5 interrupts none. 17.6 adc registers 17.6.1 control/status register (adccsr) table 91. effect of low power modes on adc mode effect wait no effect on a/d converter halt a/d converter disabled. after wake-up from halt mode, the a/d converter requires a stabilization time t stab (see section 19: electrical characteristics ) before accurate conversions can be performed. adccsr reset value: 0000 0000 (00h) 7 6 543210 eoc speed adon reserved ch[3:0] ro rw rw - rw table 92. adccsr regi ster description bit name function 7eoc end of conversion this bit is set by hardware. it is cleared by hardware when software reads the adcdrh register or writes to an y bit of the adccsr register. 0: conversion is not complete 1: conversion complete 6 speed adc clock selection this bit is set and cleared by software. 0: f adc = f cpu /4 1: f adc = f cpu /2
st72321xx-auto 10-bit a/d converter (adc) doc id 13829 rev 1 175/243 17.6.2 data register (adcdrh) 5adon a/d converter on this bit is set and cleared by software. 0: disable adc and stop conversion 1: enable adc and start conversion 4 - reserved. must be kept cleared 3:0 ch[3:0] channel selection these bits are set and cleared by software. they select the analog input to convert. 0000: channel pin = ain0 0001: channel pin = ain1 0010: channel pin = ain2 0011: channel pin = ain3 0100: channel pin = ain4 0101: channel pin = ain5 0110: channel pin = ain6 0111: channel pin = ain7 1000: channel pin = ain8 1001: channel pin = ain9 1010: channel pin = ain10 1011: channel pin = ain11 1100: channel pin = ain12 1101: channel pin = ain13 1110: channel pin = ain14 1111: channel pin = ain15 note: the number of channels is device dependent. refer to the device pinout description. table 92. adccsr register description (continued) bit name function adcdrh reset value: 0000 0000 (00h) 76543210 d[9:2] ro table 93. adcdrh regi ster description bit name function 7:0 d[9:2] msb of converted analog value
10-bit a/d converter (adc) st72321xx-auto 176/243 doc id 13829 rev 1 17.6.3 data register (adcdrl) 17.6.4 adc register map and reset values adcdrl reset value: 0000 0000 (00h) 76543210 reserved d[1:0] -ro table 94. adcdrl register description bit name function 7:2 - reserved. forced by hardware to 0. 1:0 d[1:0] lsb of converted analog value table 95. adc register map and reset values address (hex.) register label 76543210 0070h adccsr reset value eoc 0 speed 0 adon 00 ch3 0 ch2 0 ch1 0 ch0 0 0071h adcdrh reset value d9 0 d8 0 d7 0 d6 0 d5 0 d4 0 d3 0 d2 0 0072h adcdrl reset value000000 d1 0 d0 0
st72321xx-auto instruction set doc id 13829 rev 1 177/243 18 instruction set 18.1 cpu addressing modes the cpu features 17 different addressing mo des which can be classified in seven main groups as listed in the following table: the cpu instruction set is designed to minimize the number of bytes required per instruction: to do so, most of the addressing modes may be divided in two submodes called long and short: long addressing mode is more powerful because it can use the full 64 kbyte address space; however, it uses more bytes and more cpu cycles. short addressing mode is less powerful because it can generally only access page zero (0000h - 00ffh range), but the instruction size is more compact, and faster. all memory to memory instructions use shor t addressing modes only (clr, cpl, neg, bset, bres, btjt, btjf, inc, dec, rlc, rrc, sll, srl, sra, swap). the st7 assembler optimizes the use of long and short addressing modes. table 96. addressing modes group example inherent nop immediate ld a,#$55 direct ld a,$55 indexed ld a,($55,x) indirect ld a,([$55],x) relative jrne loop bit operation bset byte,#5 table 97. cpu addressing mode overview mode syntax destination pointer address (hex.) pointer size (hex.) length (bytes) inherent nop + 0 immediate ld a,#$55 + 1 short direct ld a,$10 00..ff + 1 long direct ld a,$1000 0000..ffff + 2 no offset direct indexed ld a,(x) 00..ff + 0 short direct indexed ld a,($10,x) 00..1fe + 1 long direct indexed ld a,($1000,x) 0000..ffff + 2 short indirect ld a,[$10 ] 00..ff 00..ff byte + 2 long indirect ld a,[$10.w] 0000..ffff 00..ff word + 2 short indirect indexed ld a,([ $10],x) 00..1fe 00..ff byte + 2
instruction set st72321xx-auto 178/243 doc id 13829 rev 1 18.1.1 inherent all inherent instructions consist of a single byte. the opcode fully specifies all the required information for the cpu to process the operation. long indirect indexed ld a,([$10.w ],x) 0000..ffff 00..ff word + 2 relative direct jrne loop pc+/-127 + 1 relative indirect jrne [$10] pc+/-127 00..ff byte + 2 bit direct bset $10,#7 00..ff + 1 bit indirect bset [$10], #7 00..ff 00..ff byte + 2 bit direct relative btjt $10,#7,skip 00..ff + 2 bit indirect relative btjt [$10 ],#7,skip 00..ff 00..ff byte + 3 table 97. cpu addressing mode overview (continued) mode syntax destination pointer address (hex.) pointer size (hex.) length (bytes) table 98. inherent instructions instruction function nop no operation trap s/w interrupt wfi wait for interrupt (low power mode) halt halt oscillator (lowest power mode) ret sub-routine return iret interrupt sub-routine return sim set interrupt mask (level 3) rim reset interrupt mask (level 0) scf set carry flag rcf reset carry flag rsp reset stack pointer ld load clr clear push/pop push/pop to/from the stack inc/dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement mul byte multiplication sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles
st72321xx-auto instruction set doc id 13829 rev 1 179/243 18.1.2 immediate immediate instructions have 2 bytes. the firs t byte contains the opcode and the second byte contains the operand value. 18.1.3 direct in direct instructions, the operands are referenced by their memory address. the direct addressing mode consists of two submodes: direct (short) the address is a byte, thus requires only one byte after the opcode, but only allows 00 - ff addressing space. direct (long) the address is a word, thus allowing 64 kbyte addressing space, but requires 2 bytes after the opcode. 18.1.4 indexed (no offset, short, long) in this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (x or y) with an offset. the indexed addressing mode consists of three submodes: indexed (no offset) there is no offset, (no extra byte after the opcode), and allows 00 - ff addressing space. indexed (short) the offset is a byte, thus requires only one byte after the opcode and allows 00 - 1fe addressing space. indexed (long) the offset is a word, thus allowing 64 kbyte addressing space and requires 2 bytes after the opcode. table 99. immediate instructions instruction function ld load cp compare bcp bit compare and, or, xor logical operations adc, add, sub, sbc arithmetic operations
instruction set st72321xx-auto 180/243 doc id 13829 rev 1 18.1.5 indirect (short, long) the required data byte to do the operation is found by its memory address, located in memory (pointer). the pointer address follows the opcode. the indirect addressing mode consists of two submodes: indirect (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - ff addressing space, and requires 1 byte after the opcode. indirect (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. 18.1.6 indirect indexed (short, long) this is a combination of indirect and short indexed addressing modes. the operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (x or y) with a pointer value located in memory. the pointer address follows the opcode. the indirect indexed addressing mode consists of two submodes: indirect indexed (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1fe addressing space, and requires 1 byte after the opcode. indirect indexed (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. table 100. instructions supporting direct, indexed, indirect, and indirect indexed addressing modes type instruction function long and short instructions ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic additions/subtractions operations bcp bit compare
st72321xx-auto instruction set doc id 13829 rev 1 181/243 18.1.7 relative (direct, indirect) this addressing mode is used to modify the pc register value, by adding an 8-bit signed offset to it. the relative addressing mode consists of two submodes: relative (direct) the offset is following the opcode. relative (indirect) the offset is defined in memory, which address follows the opcode. 18.2 instruction groups the st7 family devices use an instruction set co nsisting of 63 instruct ions. the instructions may be subdivided into 13 main groups as illustra ted in the following table: short instructions only clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump operations sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles call, jp call or jump subroutine table 100. instructions supporting direct, indexed, indirect, and indirect indexed addressing modes (continued) type instruction function table 101. available relative direct/indirect instructions instruction function jrxx conditional jump callr call relative table 102. instruction groups group instructions load and transfer ld clr stack operation push pop rsp increment/decrement inc dec compare and tests cp tnz bcp
instruction set st72321xx-auto 182/243 doc id 13829 rev 1 18.2.1 using a prebyte the instructions are described with one to four opcodes. in order to extend the number of available opcodes for an 8-bit cpu (256 opcodes), three different prebyte opcodes are defined. these prebytes modify the meaning of the instruction they precede. the whole instruction becomes: pc - 2 end of previous instruction pc - 1 prebyte pc opcode pc + 1 additional word (0 to 2) according to the number of bytes required to compute the effective address these prebytes enable instruction in y as well as indirect addressing modes to be implemented. they precede the opcode of the instruction in x or the instruction using direct addressing mode. the prebytes are: pdy 90 replace an x based instruction using immediate, direct, indexed, or inherent addressing mode by a y one. pix 92 replace an instruction using direct, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. it also changes an instruction using x indexed addressing mode to an instruction using indirect x indexed addressing mode. piy 91 replace an instruction using x indirect indexed addressing mode by a y one. logical operations and or xor cpl neg bit operation bset bres conditional bit test and branch btjt btjf arithmetic operations adc add sub sbc mul shift and rotates sll srl sra rlc rrc swap sla unconditional jump or call jra jrt jrf jp call callr nop ret conditional branch jrxx interruption management trap wfi halt iret condition code flag modification sim rim scf rcf table 102. instruction groups (continued) group instructions
st72321xx-auto instruction set doc id 13829 rev 1 183/243 table 103. instruction set overview mnemo description function/example dst src i1 h i0 n z c adc add with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp bit compare a, memory tst (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf jump if bit is false (0) btjf byte, #3, jmp1 m c btjt jump if bit is true (1) btjt byte, #3, jmp1 m c call call subroutine callr call subroutine relative clr clear reg, m 0 1 cp arithmetic compare tst(reg - m) reg m n z c cpl one complement a = ffh-a reg, m n z 1 dec decrement dec y reg, m n z halt halt 10 iret interrupt routine return pop cc, a, x, pc i1 h i0 n z c inc increment inc x reg, m n z jp absolute jump jp [tbl.w] jra jump relative always jrt jump relative jrf never jump jrf * jrih jump if ext. int pin = 1 (ext. int pin high) jril jump if ext. int pin = 0 (ext. int pin low) jrh jump if h = 1 h = 1 ? jrnh jump if h = 0 h = 0 ? jrm jump if i1:0 = 11 i1:0 = 11 ? jrnm jump if i1:0 <> 11 i1:0 <> 11 ? jrmi jump if n = 1 (minus) n = 1 ? jrpl jump if n = 0 (plus) n = 0 ? jreq jump if z = 1 (equal) z = 1 ? jrne jump if z = 0 (not equal) z = 0 ? jrc jump if c = 1 c = 1 ? jrnc jump if c = 0 c = 0 ? jrult jump if c = 1 unsigned < jruge jump if c = 0 jmp if unsigned >=
instruction set st72321xx-auto 184/243 doc id 13829 rev 1 jrugt jump if (c + z = 0) unsigned > jrule jump if (c + z = 1) unsigned <= ld load dst <= src reg, m m, reg n z mul multiply x,a = x * a a, x, y x, y, a 0 0 neg negate (2's compl) neg $10 reg, m n z c nop no operation or or operation a = a + m a m n z pop pop from the stack pop reg reg m pop cc cc m i1 h i0 n z c push push onto the stack push y m reg, cc rcf reset carry flag c = 0 0 ret subroutine return rim enable interrupts i1:0 = 10 (level 0) 1 0 rlc rotate left true c c <= a <= c reg, m n z c rrc rotate right true c c => a => c reg, m n z c rsp reset stack pointer s = max allowed sbc subtract with carry a = a - m - c a m n z c scf set carry flag c = 1 1 sim disable interrupts i1:0 = 11 (level 3) 1 1 sla shift left arithmetic c <= a <= 0 reg, m n z c sll shift left logic c <= a <= 0 reg, m n z c srl shift right logic 0 => a => c reg, m 0 z c sra shift right arithmetic a7 => a => c reg, m n z c sub subtraction a = a - m a m n z c swap swap nibbles a7-a4 <=> a3-a0 reg, m n z tnz test for neg & zero tnz lbl1 n z trap s/w trap s/w interrupt 1 1 wfi wait for interrupt 1 0 xor exclusive or a = a xor m a m n z table 103. instruction set overview (continued) mnemo description function/example dst src i1 h i0 n z c
st72321xx-auto electrical characteristics doc id 13829 rev 1 185/243 19 electrical characteristics 19.1 parameter conditions unless otherwise specified, all voltages are referred to v ss . 19.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25c and t a =t amax (given by the selected temperature range). data based on characterization results, desi gn simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3 ? ). 19.1.2 typical values unless otherwise specified, typical data is based on t a =25c, v dd = 5v. the typical values are given only as design guidelines and are not tested. 19.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 19.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 71 . figure 71. pin loading conditions 19.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 72 . figure 72. pin input voltage c l st7 pin v in st7 pin
electrical characteristics st72321xx-auto 186/243 doc id 13829 rev 1 19.2 absolute maximum ratings stresses above those listed as ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 19.2.1 voltage characteristics table 104. voltage characteristics symbol ratings maximum value unit v dd - v ss supply voltage 6.5 v v pp - v ss programming voltage 13 v in (1) input voltage on true open-drain pin v ss - 0.3 to 6.5 input voltage on any other pin v ss - 0.3 to v dd +0.3 | ? v ddx | and | ? v ssx | variations between different digital power pins 50 mv |v ssa - v ssx | variations between digital and analog ground pins 50 v esd(hbm) electrostatic discharge voltage (human body model) see section 19.7.3 on page 202 . v esd(mm) electrostatic discharge voltage (machine model) 1. directly connecting the reset and i/o pins to v dd or v ss could damage the device if an unint entional internal reset is generated or an unexpected change of the i/o c onfiguration occurs (for example, du e to a corrupted program counter). to guarantee safe operation, this connecti on has to be done through a pull-up or pull-down resistor (typical: 4.7k ? for reset, 10k ? for i/os). for the same reason, unused i/o pins must not be directly tied to v dd or v ss .
st72321xx-auto electrical characteristics doc id 13829 rev 1 187/243 19.2.2 current characteristics 19.2.3 thermal characteristics table 105. current characteristics symbol ratings maximum value unit i vdd total current into v dd power lines (source) (1) 1. all power (v dd ) and ground (v ss ) lines must always be connect ed to the external supply. 150 ma i vss total current out of v ss ground lines (sink) (1) i io (2) 2. directly connecting the reset and i/o pins to v dd or v ss could damage the device if an unintentional internal reset is generated or an unexpected change of the i/o configuration occurs (for example, due to a corrupted program counter). to guarantee safe operatio n, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7k ? for reset, 10k ? for i/os). for the same reason, unused i/o pins must not be directly tied to v dd or v ss . output current sunk by any standard i/o and control pin 25 ma output current sunk by any high sink i/o pin 50 output current source by any i/os and control pin - 25 i inj(pin) (3)(4) 3. i inj(pin) must never be exceeded. this is implicitly ensured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in electrical characteristics st72321xx-auto 188/243 doc id 13829 rev 1 19.3 operating conditions 19.3.1 general operating conditions note: some temperature ranges are only available with a specific package and memory size. refer to section 21: device configuration and ordering information on page 223 . figure 73. f cpu max versus v dd table 107. general operating conditions symbol parameter conditions min max unit f cpu internal clock frequency 0 8 mhz v dd standard voltage range (except flash write/erase) 3.8 5.5 v operating voltage for flash write/erase v pp = 11.4 to 12.6v 4.5 5.5 t a ambient temperature range a suffix version -40 85 c b suffix version 105 c suffix version 125 f cpu [mhz] supply voltage [v] 8 4 2 1 0 3.5 4.0 4.5 5.5 functionality functionality guaranteed in this area not guaranteed in this area 3.8 6 (unless otherwise specified in the tables of parametric data)
st72321xx-auto electrical characteristics doc id 13829 rev 1 189/243 19.3.2 operating conditions with low voltage detector (lvd) subject to general operating conditions for v dd , f cpu , and t a . 19.3.3 auxiliary voltage detector (avd) thresholds subject to general operating conditions for v dd , f cpu , and t a . table 108. operating conditions with low voltage detector (lvd) symbol parameter conditions min typ max unit v it+(lvd) reset release threshold (v dd rise) vd level = high in option byte 4.0 (1) 4.2 4.5 v vd level = med. in option byte (2) 3.55 (1) 3.75 4.0 (1) vd level = low in option byte (2) 2.95 (1) 3.15 3.35 (1) v it-(lvd) reset generation threshold (v dd fall) vd level = high in option byte 3.8 4.0 4.25 (1) vd level = med. in option byte (2) 3.35 (1) 3.55 3.75 (1) vd level = low in option byte (2) 2.8 (1) 3.0 3.15 (1) v hys(lvd) lvd voltage threshold hysteresis v it+(lvd) -v it-(lvd) 200 mv vt por v dd rise time (2)(3) lvd enabled 6s/v 100ms/v - t g(vdd) v dd glitches filtered (not detected) by lvd (4) 40 ns 1. data based on characterization results, tested in production for rom devices only 2. data based on characterization results, not tested in production 3. when vt por is faster than 100s/v, the re set signal is released after a delay of maximum 42s after v dd crosses the v it+(lvd) threshold. 4. if the medium or low thresholds are selected, the detecti on may occur outside the specified operating voltage range. below 3.8v, device operation is not guaranteed. table 109. auxiliary voltage detector (avd) thresholds symbol parameter conditions min typ max unit v it+(avd) 1 ? 0 avdf flag toggle threshold (v dd rise) vd level = high in option byte 4.4 (1) 4.6 4.9 (1) v vd level = med. in option byte 3.95 (1) 4.15 4.4 (1) vd level = low in option byte 3.4 (1) 3.6 3.8 (1) v it-(avd) 0 ? 1 avdf flag toggle threshold (v dd fall) vd level = high in option byte 4.2 (1) 4.4 4.65 (1) vd level = med. in option byte 3.75 (1) 4.0 4.2 (1) vd level = low in option byte 3.2 (1) 3.4 3.6 (1) v hys(avd) avd voltage threshold hysteresis v it+(avd) -v it-(avd) 200 mv ? v it- voltage drop between avd flag set and lvd reset activated v it-(avd) -v it-(lvd) 450 1. data based on characterization results, tested in production for rom devices only
electrical characteristics st72321xx-auto 190/243 doc id 13829 rev 1 19.3.4 external voltage detector (evd) thresholds subject to general operating conditions for v dd , f cpu , and t a . table 110. external voltage detector (evd) thresholds symbol parameter conditions min typ max unit v it+(evd) 1 ? 0 avdf flag toggle threshold (v dd rise (1) 1.15 1.26 1.35 v v it-(evd) 0 ? 1 avdf flag toggle threshold (v dd fall) (1) 1.1 1.2 1.3 v hys(evd) evd voltage threshold hysteresis v it+(evd) -v it-(evd) 200 mv 1. data based on characterization results, not tested in production
st72321xx-auto electrical characteristics doc id 13829 rev 1 191/243 19.4 supply current characteristics the following current consumption specified for the st7 functional operating modes over temperature range does not take into account the clock source current consumption. to obtain the total device consumption, the two current values must be added (except for halt mode, for which the clock is stopped). 19.4.1 current consumption table 111. current consumption symbol parameter conditions flash devices rom devices unit typ max (1) typ max (1) i dd supply current in run mode (2) f osc = 2mhz, f cpu =1mhz f osc = 4 mhz, f cpu =2mhz f osc = 8 mhz, f cpu =4mhz f osc =16mhz, f cpu =8mhz 1.3 2.0 3.6 7.1 3.0 5.0 8.0 15.0 1.3 2.0 3.6 7.1 2.0 3.0 5.0 10.0 ma supply current in slow mode (2) f osc = 2 mhz, f cpu =62.5khz f osc = 4 mhz, f cpu = 125 khz f osc = 8 mhz, f cpu = 250 khz f osc =16mhz, f cpu = 500 khz 600 700 800 1100 2700 3000 3600 4000 600 700 800 1100 1800 2100 2400 3000 a supply current in wait mode (2) f osc = 2 mhz, f cpu =1mhz f osc = 4 mhz, f cpu =2mhz f osc = 8 mhz, f cpu =4mhz f osc =16mhz, f cpu =8mhz 1.0 1.5 2.5 4.5 3.0 4.0 5.0 7.0 1.0 1.5 2.5 4.5 1.3 2.0 3.3 6.0 ma supply current in slow wait mode (2) f osc = 2 mhz, f cpu =62.5khz f osc = 4 mhz, f cpu = 125 khz f osc = 8 mhz, f cpu = 250 khz f osc =16mhz, f cpu = 500 khz 580 650 770 1050 1200 1300 1800 2000 70 100 200 350 200 300 600 1200 a supply current in halt mode (3) -40c < t a < +85c <1 10 <1 10 a -40c < t a < +125c <1 50 <1 50 i dd supply current in active halt mode (4) f osc =2mhz f osc =4mhz f osc =8mhz f osc =16mhz 80 160 325 650 no max. guaran- teed 80 160 325 650 no max. guaran- teed a 1. data based on characterization results, tested in production at v dd max. and f cpu max. 2. measurements are done in the following conditions: - program executed from ram, cpu running with ram access. t he increase in consumption when executing from flash is 50%. - all i/o pins in input mode with a static value at v dd or v ss (no load) - all peripherals in reset state. - lvd disabled. - clock input (osc1) driven by external square wave. - in slow and slow wait mode, f cpu is based on f osc divided by 32. - to obtain the total current consumption of the device, add the clock source ( section 19.4.2 ) and the peripheral power consumption ( section 19.4.3 ). 3. all i/o pins in push-pull 0 mode (when applicable) with a static value at v dd or vss (no load), lvd disabled. data based on characterization results, tested in production at v dd max. and f cpu max. 4. data based on characterization results, not tested in producti on. all i/o pins in push-pull 0 mode (when applicable) with a static value at v dd or v ss (no load); clock input (osc1) dr iven by external square wave, lv d disabled. to obtain the total current consumption of the device, add the clock source consumption ( section 19.4.2 ).
electrical characteristics st72321xx-auto 192/243 doc id 13829 rev 1 power consumption vs f cpu : flash devices figure 74. typical i dd in run mode figure 75. typical i dd in slow mode figure 76. typical i dd in wait mode 0 1 2 3 4 5 6 7 8 9 3.2 3.6 4 4.4 4.8 5.2 5.5 vdd (v) idd (ma) 8mhz 4mhz 2mhz 1mhz 0.00 0.20 0.40 0.60 0.80 1.00 1.20 3.2 3.6 4 4.4 4.8 5.2 5.5 vdd (v) idd (ma) 500khz 250khz 125khz 62.5khz 0 1 2 3 4 5 6 3.2 3.6 4 4.4 4.8 5.2 5.5 vdd (v) idd (ma) 8mhz 4mhz 2mhz 1mhz
st72321xx-auto electrical characteristics doc id 13829 rev 1 193/243 figure 77. typical i dd in slow wait mode 19.4.2 supply and clock managers the previous current consumption specified for the st7 functional operating modes over temperature range does not take into account the clock source current consumption. to obtain the total device consumption, the two current values must be added (except for halt mode). 0.00 0.20 0.40 0.60 0.80 1.00 1.20 3.2 3.6 4 4.4 4.8 5.2 5.5 vdd (v) idd (ma) 500khz 250khz 125khz 62.5khz table 112. oscillators,pll and lvd current consumption symbol parameter conditions typ max unit i dd(rcint) supply current of internal rc oscillator 625 a i dd(res) supply current of resonator oscillator (1)(2) 1. data based on characterizati on results done with the extern al components specified in section 19.5.3 , not tested in production 2. as the oscillator is based on a current source, the cons umption does not depend on the voltage. see section 19.5.3 on page 196 i dd(pll) pll supply current v dd = 5v 360 i dd(lvd) lvd supply current 150 300
electrical characteristics st72321xx-auto 194/243 doc id 13829 rev 1 19.4.3 on-chip peripherals measured on lqfp64 generic board t a = 25c, f cpu =4mhz. table 113. on-chip peripherals current consumption symbol parameter conditions typ unit i dd(tim) 16-bit timer supply current (1) 1. data based on a differential i dd measurement between reset configur ation (timer counter running at f cpu /4) and timer counter stopped (only timd bit set). data valid for one timer. v dd ? 5.0v 50 a i dd(art) art pwm supply current (2) 2. data based on a differential i dd measurement between reset confi guration (timer stopped) and timer counter enabled (only tce bit set). v dd ? 5.0v 75 a i dd(spi) spi supply current (3) 3. data based on a differential i dd measurement between reset configurat ion (spi disabled) and a permanent spi master communication at maximum speed (data se nt equal to 55h). this measurement includes the pad toggling consumption. v dd ? 5.0v 400 a i dd(sci) sci supply current (4) 4. data based on a differential i dd measurement between sci low power state (scid = 1) and a permanent sci data transmit sequence. i dd(i2c) i2c supply current (5) 5. data based on a differential i dd measurement between reset configurat ion (i2c disabled) and a permanent i2c master communication at 100 khz (data sent equal to 55h). this measurement includes the pad toggling consumption (27k ohm exte rnal pull-up on clock and data lines). v dd ? 5.0v 175 a i dd(adc) adc supply current when converting (6) 6. data based on a differential i dd measurement between reset configuration and continuous a/d conversions. v dd ? 5.0v 400 a
st72321xx-auto electrical characteristics doc id 13829 rev 1 195/243 19.5 clock and timing characteristics subject to general operating conditions for v dd , f cpu , and t a . 19.5.1 general timings 19.5.2 external clock source figure 78. typical application with an external clock source table 114. general timings symbol parameter conditions min typ (1) 1. data based on typical application software. max unit t c(inst) instruction cycle time 2312t cpu f cpu = 8 mhz 250 375 1500 ns t v(it) interrupt reaction time (2) t v(it) = ? t c(inst) + 10 2. time measured between interrupt event and interrupt vector fetch. ? t c(inst) is the number of t cpu cycles needed to finish the current instruction execution. 10 22 t cpu f cpu =8mhz 1.25 2.75 s table 115. external clock source symbol parameter conditions min typ max unit v osc1h osc1 input pin high level voltage see figure 78 0.7xv dd v dd v v osc1l osc1 input pin low level voltage v ss 0.3xv dd t w(osc1h) t w(osc1l) osc1 high or low time (1) 1. data based on design simulation and/or technology characteristics, not tested in production. 5 ns t r(osc1) t f(osc1) osc1 rise or fall time (1) 15 i lkg osc1 input leakage current v ss < v in < v dd 1 a osc1 osc2 f osc external st72xxx clock source not connected internally v osc1l v osc1h t r(osc1) t f(osc1) t w(osc1h) t w(osc1l) i lkg 90% 10%
electrical characteristics st72321xx-auto 196/243 doc id 13829 rev 1 19.5.3 crystal and ceramic resonator oscillators the st7 internal clock can be supplied with four different crystal/ceramic resonator oscillators. all the information given in this pa ragraph is based on characterization results with specified typical external components. in the application, the resonator and the load capacitors have to be placed as close as possibl e to the oscillator pins in order to minimize output distortion and start-up stabilization time. refer to t he crystal/ceramic resonator manufacturer for more details (such as frequency, package or accuracy). figure 79. typical application with a crystal or ceramic resonator) table 116. crystal and ceramic resonator oscillators symbol parameter conditions min typ max unit f osc oscillator frequency (1) 1. the oscillator selection can be optimized in terms of supply current using a high-quality resonator with small r s value. refer to crystal/ceramic re sonator manufacturer for more details. lp: low power oscillator mp: medium power oscillator ms: medium speed oscillator hs: high speed oscillator 1 >2 >4 >8 - 2 4 8 16 mhz r f feedback resistor (2) 2. data based on characterization results, not tested in pr oduction. the relatively low value of the rf resistor offers a good protection against issues resulting fr om use in a humid environment, due to the induced leakage and the bias condition change. however, it is re commended to take this point into account if the microcontroller is used in tough humidity conditions. -20-40k ? c l1 c l2 recommended load capacitance versus equivalent serial resistance of the crystal or ceramic resonator (r s ) (3) 3. for c l1 and c l2 it is recommended to use high-quality ceramic capacitors in the 5pf to 25pf range (typ.) designed for high-frequency applications and selected to match th e requirements of the crystal or resonator. c l1 and c l2, are usually the same size. the crystal manufacturer typica lly specifies a load capacitance which is the se ries combination of c l1 and c l2 . pcb and mcu pin capacitance must be included when sizing c l1 and c l2 (10pf can be used as a rough estimate of the combined pin and board capacitance). r s =200 ? r s =200 ? r s =200 ? r s =100 ? lp oscillator mp oscillator ms oscillator hs oscillator 22 22 18 15 - 56 46 33 33 pf i 2 osc2 driving current v dd =5v, v in =v ss lp oscillator mp oscillator ms oscillator hs oscillator - 80 160 310 610 150 250 460 910 a osc2 osc1 f osc c l1 c l2 i 2 r f st72xxx resonator when resonator with integrated capacitors
st72321xx-auto electrical characteristics doc id 13829 rev 1 197/243 19.5.4 rc oscillators figure 80. typical f osc(rcint) versus t a note: to reduce disturbance to the rc oscillator, it is re commended to place decoupling capacitors between v dd and v ss as shown in figure 100 . table 117. oscrange selecti on for typical resonators supplier f osc (mhz) typical ceramic resonators (1) 1. resonator characteri stics given by the ceramic resonator manufacturer. for more information on these resonators, please consult www.murata.com. reference recommended oscrange option bit configuration murata 2 cstcc2m00g56a-r0 mp mode (2) 2. lp mode is not recommended for 2 mhz resonator because the peak to peak amplitude is too small (> 0.8v). 4 cstcr4m00g55b-r0 ms mode 8 cstce8m00g55a-r0 hs mode 16 cstce16m0g53a-r0 table 118. rc oscillator characteristics symbol parameter conditions min typ max unit f osc(rcint) internal rc oscillator frequency (see figure 80 ) t a =25c, v dd =5v 2 3.5 5.6 mhz 3 3.2 3.4 3.6 3.8 4 -45 0 25 70 130 t a (c) f osc(rcint) (mhz) vdd = 5v vdd = 5.5v
electrical characteristics st72321xx-auto 198/243 doc id 13829 rev 1 19.5.5 pll characteristics the user must take the pll jitter into account in the application (for example, in serial communication or sampling of high frequency signals). the pll jitter is a periodic effect, which is integrated over several cpu cycles. therefore, the longer the period of the application signal, the less it is impacted by the pll jitter. figure 81 shows the pll jitter integrated on application signals in the range 125 khz to 4 mhz. at frequencies of less than 125 khz, the jitter is negligible. figure 81. integrated pll jitter versus signal frequency (1) 1. measurement conditions: f cpu = 8 mhz table 119. pll characteristics symbol parameter conditions min typ max unit f osc pll input frequency range 2 4 mhz ? f cpu /f cpu instantaneous pll jitter (1) 1. data based on characterization results f osc = 4 mhz 1.0 2.5 % f osc = 2 mhz 2.5 4.0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 4 mhz 2 mhz 1 mhz 500 khz 250 khz application frequency +/-jitter (%)
st72321xx-auto electrical characteristics doc id 13829 rev 1 199/243 19.6 memory characteristics 19.6.1 ram and hardware registers 19.6.2 flash memory warning: do not connect 12v to v pp before v dd is powered on, as this may damage the device. table 120. ram supply voltage symbol parameter conditions min typ max unit v rm data retention mode (1) 1. minimum v dd supply voltage without losing data stored in ram (in halt mode or under reset) or in hardware register s (only in halt mode). not tested in production. halt mode (or reset) 1.6 v table 121. dual voltage hdflash memory symbol parameter conditions min (1) 1. data based on characterization results, not tested in production typ max (1) unit f cpu operating frequency read mode 0 8 mhz write / erase mode 1 8 v pp programming voltage (2) 2. v pp must be applied only during the programming or eras ing operation and not permanently for reliability reasons. 4.5v < v dd < 5.5v 11.4 12.6 v i dd supply current (3) 3. data based on simulation results, not tested in production run mode (f cpu = 4 mhz) 3 ma write / erase 0 power down mode / halt 1 10 a i pp v pp current (3) read (v pp = 12v) 200 write / erase 30 ma t vpp internal v pp stabilization time 10 s t ret data retention t a =55c 20 years n rw write erase cycles t a = 85c 100 cycles t prog t erase programming or erasing temperature range -40 25 85 c
electrical characteristics st72321xx-auto 200/243 doc id 13829 rev 1 19.7 emc (electromagnetic co mpatibility) characteristics susceptibilitytests ar e performed on a sample basis during product characterization. 19.7.1 functional ems (elect romagnetic susceptibility) based on a simple running application on the product (toggling two leds through i/o ports), the product is stressed by two electromagnetic ev ents until a failure occurs (indicated by the leds). esd : electrostatic discharge (positive and negati ve) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 1000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100pf capacitor until a functional disturbance occurs. this test conforms with the iec 1000-4-4 standard. a device reset allows normal operations to be resumed. the test results given in table 122 below are based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations the software flowchart must include the management of runaway conditions such as: corrupted program counter unexpected reset critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forc ing a low state on the reset pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015).
st72321xx-auto electrical characteristics doc id 13829 rev 1 201/243 . 19.7.2 emi (electromagnetic interference) based on a simple application running on the product (toggling two leds through the i/o ports), the product is monitored in terms of emi ssion. this emission test is in line with the norm sae j 1752/3 which sp ecifies the boar d and the loading of each pin. table 122. ems test results symbol parameter conditions level/class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance flash device: v dd ? 5v, t a ? +25c, f osc ? 8mhz, conforms to iec 1000-4-2 4b rom device: v dd ? 5v, t a ? +25c, f osc ? 8 mhz, conforms to iec 1000-4-2 4a v fftb fast transient voltage bu rst limits to be applied through 100pf on v dd and v dd pins to induce a functional disturbance v dd ? 5v, t a ? +25c, f osc ? 8 mhz, conforms to iec 1000-4-4 3b table 123. emi emissions symbol parameter conditions monitored frequency band max vs [f osc /f cpu ] (1) unit v dd ? 5v, t a ? +25c, conforming to sae j 1752/3 8/4 mhz 16/8 mhz s emi peak level 60 kbyte flash devices in lqfp64 package 0.1 mhz to 30 mhz 15 20 dbv 30 mhz to 130 mhz 20 27 130mhz to 1ghz 0 5 sae emi level 2.5 3 - 1. data based on characterization results, not tested in production.
electrical characteristics st72321xx-auto 202/243 doc id 13829 rev 1 19.7.3 absolute maximum rati ngs (electrical sensitivity) based on two different tests (esd and lu) using specific measurement methods, the product is stressed in order to determine its per formance in terms of electrical sensitivity. for more details, refer to the application note an1181. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). two models can be simulated: human body model and machine model. this test conforms to the jesd22-a114a/a115a standard. static latch-up (lu) two complementary static tests are required on six parts to assess the latch-up performance: a supply overvoltage is applied to each power supply pin. a current injection is applied to each input, output and configurable i/o pin. these tests are compliant with the eia/jesd 78 ic latch-up standard. table 124. esd absolute maximum ratings symbol ratings conditions max. value (1) 1. data based on characterization results, not tested in production. unit v esd(hbm) electrostatic discharge voltage (human body model) t a ? +25c 2000 v v esd(mm) electrostatic discharge voltage (machine model) 200 table 125. electrical sensitivities symbol parameter conditions class (1) 1. class description: a class is an stmi croelectronics internal specification. all its limits are higher than the jedec specifications, that means when a device belongs to class a it exceeds the jedec standard. b class strictly covers all the jede c criteria (international standard). lu static latch-up class t a ? +25c t a ? +85c t a ? +125c a a a
st72321xx-auto electrical characteristics doc id 13829 rev 1 203/243 19.8 i/o port pin characteristics 19.8.1 general characteristics subject to general operating conditions for v dd, f osc , and t a unless otherwise specified. table 126. i/o port pin general characteristics symbol parameter conditions min typ max unit v il input low level voltage (1) cmos ports 0.3xv dd v v ih input high level voltage (1) 0.7xv dd v hys schmitt trigger voltage hysteresis (2) 0.7 i inj(pin) (3) injected current on pc 6 pin (flash devices only) v dd =5v 0+4 ma injected current on an i/o pin 4 ? i inj(pin) (3) total injected current (sum of all i/o and control pins) 25 i l input leakage current v ss < v in < v dd 1 a i s static current consumption floating input mode (4) 400 r pu weak pull-up equivalent resistor (5) v in =v ss v dd = 5v 50 120 250 k ? c io i/o pin capacitance 5 pf t f(io)out output high to low level fall time (1) c l = 50pf between 10% and 90% 25 ns t r(io)out output low to high level rise time (1) 25 t w(it)in external interrupt pulse time (6) 1t cpu 1. data based on characterization results, not tested in production. 2. hysteresis voltage between schmitt trigger switchin g levels. based on characterization results, not tested. 3. when the current limitation is not possible, the v in maximum must be respected, otherwise refer to i inj(pin) specification. a positive injection is induced by v in >v dd while a negative injection is induced by v in electrical characteristics st72321xx-auto 204/243 doc id 13829 rev 1 19.8.2 output driving current subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. figure 82. unused i/o pins configured as input figure 83. typical i pu vs v dd with v in =v ss 10k ? st7xxx 10k ? unused i/o port st7xxx v dd note: i/o can be left unconnected if it is configured as output greater emc robustness and lower cost. (0 or 1) by the software. this has the advantage of unused i/o port 0 10 20 30 40 50 60 70 80 90 2 2.5 3 3.5 4 4.5 5 5.5 6 vdd(v) ipu(ua) ta=140c ta=95c ta=25c ta=-45c table 127. output driving current symbol parameter conditions min max unit v ol (1) output low level voltage for a standard i/o pin when 8 pins are sunk at same time (see figure 84 ) v dd =5v i io =+5ma 1.2 v i io =+2ma 0.5 output low level voltage for a high sink i/o pin when 4 pins are sunk at same time (see figure 85 and figure 87 ) i io = +20ma, t a < 85c t a > 85c 1.3 1.5 i io =+8ma 0.6 v oh (2) output high level voltage for an i/o pin when 4 pins are sourced at same time (see figure 86 and figure 89 ) i io =-5ma, t a < 85c t a > 85c v dd -1.4 v dd -1.6 i io =-2ma v dd -0.7 1. the i io current sunk must always respect the absolute maximum rating specified in section 19.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vss . 2. the i io current sourced must always respect the absolute maximum rating specified in section 19.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vdd . true open-drain i/o pins do not have v oh .
st72321xx-auto electrical characteristics doc id 13829 rev 1 205/243 figure 84. typical v ol at v dd = 5v (standard) figure 85. typical v ol at v dd = 5v (high-sink) figure 86. typical v oh at v dd =5v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 0.005 0.01 0.015 ii o(a ) vol (v) at vdd=5v ta =14 0c " ta =95 c ta =25 c ta =-45 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.01 0.02 0.03 ii o (a ) vol(v) at vdd=5v ta= 140c ta= 95 c ta= 25 c ta= -45c 2 2.5 3 3.5 4 4.5 5 5.5 -0.01 -0.008 -0.006 -0.004 -0.002 0 ii o ( a ) vdd-voh (v) at vdd=5v v dd= 5v 140c min v dd= 5v 95c min v dd= 5v 25c min v dd= 5v -45c min
electrical characteristics st72321xx-auto 206/243 doc id 13829 rev 1 figure 87. typical v ol versus v dd (standard) figure 88. typical v ol versus v dd (high-sink) figure 89. typical v dd -v oh versus v dd 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 2 2.5 3 3.5 4 4.5 5 5.5 6 vdd(v) vol(v) at iio=5ma ta= -4 5c ta= 25c ta= 95c ta= 140 c 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 2 2.5 3 3.5 4 4.5 5 5.5 6 vdd(v) vol(v) at iio=2ma ta=-45c ta=25c ta=95c ta=140c 0 0.1 0.2 0.3 0.4 0.5 0.6 22.533.544.555.56 vdd(v) vol(v) at iio=8ma ta= 140c ta=95c ta=25c ta=-45c 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 22.533.544.555.56 v dd(v ) vol(v) at iio=20ma ta = 140 c ta =95 c ta =25 c ta =-45c 0 1 2 3 4 5 6 2 2.5 3 3.5 4 4.5 5 5.5 6 vdd(v) vdd-voh(v) at iio=-5m a ta= -45c ta= 25c ta= 95c ta= 140c 2 2.5 3 3.5 4 4.5 5 5.5 2 2.5 3 3.5 4 4.5 5 5.5 6 vdd(v) vdd-voh(v) at iio=-2ma ta= -45c ta= 25c ta= 95c ta= 140c
st72321xx-auto electrical characteristics doc id 13829 rev 1 207/243 19.9 control pin characteristics 19.9.1 asynchronous reset pin subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. table 128. asynchronous reset pin characteristics symbol parameter conditions min typ max unit v il input low level voltage (1) 0.16xv d d v v ih input high level voltage (1) 0.85xv d d v hys schmitt trigger voltage hysteresis (2) 2.5 v ol output low level voltage (3) v dd =5v, i io = +2ma 0.2 0.5 i io input current on reset pin 2 ma r on weak pull-up equivalent resistor 20 30 120 k ? t w(rstl)out generated reset pulse duration stretch applied on external pulse 0 42 (4) s internal reset sources 20 30 42 (4) t h(rstl)in external reset pulse hold time (5) 2.5 t g(rstl)in filtered glitch duration (6) 200 ns 1. data based on characterization results, not tested in production. 2. hysteresis voltage between schmitt trigger switching levels. 3. the i io current sunk must always respect the absolute maximum rating specified in section 19.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vss . 4. data guaranteed by design, not tested in production. 5. to guarantee the reset of the device, a minimum pulse has to be applied to the reset pin. all short pulses applied on the reset pin with a duration below t h(rstl)in can be ignored. 6. the reset network (the resistor and two capacitors) protec ts the device against parasitic resets, especially in noisy environments.
electrical characteristics st72321xx-auto 208/243 doc id 13829 rev 1 figure 90. reset pin protection when lvd is enabled note: 1 the reset network protects the device against parasitic resets. the output of the external reset circuit must have an open-drain output to drive the st7 reset pad. otherwise the device can be damaged when the st7 generates an internal reset (lvd or watchdog). whether the reset source is internal or external, the user must ensure that the level on the reset pin can go below the v il maximum level specified in section 19.9.1 on page 207 . otherwise the reset w ill not be taken into account internally. because the reset circuit is designed to allow the internal reset to be output in the reset pin, the user must ensure that the current sunk on the reset pin is less than the absolute maximum value specified for i inj(reset) in section 19.2.2 on page 187 . 2 when the lvd is enabled, it is recommended not to connect a pull-up resistor or capacitor. a 10nf pull-down capacitor is required to filter noise on the reset line. 3 in case a capacitive power supply is used, it is recommended to connect a 1m ? pull-down resistor to the reset pin to discharge any residual voltage induced by the capacitive effect of the power supply (this will add 5a to the power consumption of the mcu). 4 tips when using the lvd: a. check that all recommendations related to reset circuit have been applied (see notes above). b. check that the power supply is properly decoupled (100nf + 10f close to the mcu). refer to an1709 and an2017. if this cannot be done, it is recommended to put a 100nf + 1m ? pull-down on the reset pin. c. the capacitors connected on the reset pin and also the power supply are key to avoid any start-up marginality. in most cases, st eps a and b above are sufficient for a robust solution. otherwise, replace 10nf pull-down on the reset pin with a 5f to 20f capacitor. 0.01f st72xxx pulse generator filter r on v dd watchdog lvd reset internal reset reset external required 1m ? optional (note 3)
st72321xx-auto electrical characteristics doc id 13829 rev 1 209/243 figure 91. reset pin protection when lvd is disabled note: the reset network protects the device against parasitic resets. the output of the external reset circuit must have an open-drain output to drive the st7 reset pad. otherwise the device can be damaged when the st7 generates an internal reset (lvd or watchdog). whether the reset source is internal or external, the user must ensure that the level on the reset pin can go below the v il maximum level specified in section 19.9.1 on page 207 . otherwise the reset w ill not be taken into account internally. because the reset circuit is designed to allow the internal reset to be output in the reset pin, the user must ensure that the current sunk on the reset pin is less than the absolute maximum value specified for i inj(reset) in section 19.2.2 on page 187 . 19.9.2 iccsel/v pp pin subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. 0.01f external reset circuit user required st72xxx pulse generator filter r on v dd watchdog internal reset table 129. iccsel/v pp pin characteristics symbol parameter conditions min max unit v il input low level voltage (1) 1. data based on design simulation and/or technology characteristics, not tested in production. flash versions v ss 0.2 v rom versions v ss 0.3xv dd v ih input high level voltage (1) flash versions v dd -0.1 12.6 rom versions 0.7xv dd v dd i l input leakage current v in =v ss 1 a
electrical characteristics st72321xx-auto 210/243 doc id 13829 rev 1 figure 92. two typical applications with iccsel/v pp pin (1) 1. when icc mode is not required by the application, the iccsel/v pp pin must be tied to v ss . 19.10 timer peripheral characteristics subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. refer to section 19.8: i/o port pin characteristics for more details on the input/output alternate function characteristi cs (such as output compare, input capture, external clock, or pwm output). iccsel/v pp st72xxx 10k ? programming tool v pp st72xxx table 130. 8-bit pwm-art auto-reload timer characteristics symbol parameter conditions min typ max unit t res(pwm) pwm resolution time 1t cpu f cpu =8mhz 125 ns f ext art external clock frequency 0f cpu /2 mhz f pwm pwm repetition rate res pwm pwm resolution 8 bit v os pwm/dac output step voltage v dd =5v, resolution = 8 bits 20 mv table 131. 16-bit timer characteristics symbol parameter conditions min typ max unit t w(icap)in input capture pulse time 1 t cpu t res(pwm) pwm resolution time 2t cpu f cpu = 8 mhz 250 ns f ext timer external clock frequency 0f cpu /4 mhz f pwm pwm repetition rate res pwm pwm resolution 16 bit
st72321xx-auto electrical characteristics doc id 13829 rev 1 211/243 19.11 communication interface characteristics 19.11.1 spi (serial peripheral interface) subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. refer to section 19.8: i/o port pin characteristics for more details on the input/output alternate function characteristics (ss , sck, mosi, miso). table 132. spi characteristics symbol parameter conditions min max unit f sck 1/t c(sck) spi clock frequency master, f cpu =8mhz f cpu /128 = 0.0625 f cpu /4 = 2 mhz slave, f cpu =8mhz 0 f cpu /2 = 4 t r(sck) t f(sck) spi clock rise and fall time see i/o port pin description t su(ss ) (1) ss setup time (2) slave t cpu + 50 ns t h(ss ) (1) ss hold time slave 120 t w(sckh) (1) t w(sckl) (1) sck high and low time master slave 100 90 t su(mi) (1) t su(si) (1) data input setup time master slave 100 100 t h(mi) (1) t h(si) (1) data input hold time master slave 100 100 t a(so) (1) data output access time slave 0 120 t dis(so) (1) data output disable time slave 240 t v(so) (1) data output valid time slave (after enable edge) 120 t h(so) (1) data output hold time 0 t v(mo) (1) data output valid time master (after enable edge) 120 t cpu t h(mo) (1) data output hold time 0 1. data based on design simulation and/or char acterization results, not tested in production. 2. depends on f cpu . for example, if f cpu = 8 mhz, then t cpu = 1 / f cpu = 125 ns and t su(ss ) = 175 ns.
electrical characteristics st72321xx-auto 212/243 doc id 13829 rev 1 figure 93. spi slave ti ming diagram with cpha = 0 (1) 1. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . 2. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate function capability releas ed. in this case, the pin status depends on the i/o port configuration. figure 94. spi slave ti ming diagram with cpha = 1 (1) 1. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . 2. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate function capability released. in this case, the pin status depends of the i/o port configuration. ss input sck input cpha=0 mosi input miso output cpha=0 t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t v(so) t a(so) t su(si) t h(si) msb out msb in bit6 out lsb in lsb out see note 2 cpol=0 cpol=1 t su(ss ) t h(ss ) t dis(so) t h(so) see note 2 bit1 in ss input sck input cpha=1 mosi input miso output cpha=1 t w(sckh) t w(sckl) t r(sck) t f(sck) t a(so) t su(si) t h(si) msb out bit6 out lsb out see cpol=0 cpol=1 t su(ss ) t h(ss ) t dis(so) t h(so) see note 2 note 2 t c(sck) hz t v(so) msb in lsb in bit1 in
st72321xx-auto electrical characteristics doc id 13829 rev 1 213/243 figure 95. spi master timing diagram (1) 1. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . 2. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate function capability released. in this case, the pin status depends of the i/o port configuration. ss input sck input cpha = 0 mosi output miso input cpha = 0 cpha = 1 cpha = 1 t c(sck) t w(sckh) t w(sckl) t h(mi) t su(mi) msb in msb out bit6 in bit6 out lsb out lsb in see note 2 see note 2 cpol = 0 cpol = 1 cpol = 0 cpol = 1 t r(sck) t f(sck) t h(mo) t v(mo)
electrical characteristics st72321xx-auto 214/243 doc id 13829 rev 1 19.11.2 i 2 c - inter ic control interface subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. refer to section 19.8: i/o port pin characteristics for more details on the input/output alternate function characteristics (sdai an d scli). the st7 i2c interface meets the requirements of the standard i2c communication protocol described in the following table. table 133. i 2 c control interface characteristics symbol parameter standard mode i 2 cfast mode i 2 c (1) unit min (2) max (2) min (2) max (2) t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0 (3) 0 (4) 900 (3) t r(sda) t r(scl) sda and scl rise time 1000 20+0.1c b 300 t f(sda) t f(scl) sda and scl fall time 300 t h(sta) start condition hold time 4.0 0.6 s t su(sta) repeated start condition setup time 4.7 t su(sto) stop condition setup time 4.0 t w(sto:sta) stop to start condition time (bus free) 4.7 1.3 c b capacitive load for each bus line 400 400 pf 1. at 4 mhz f cpu , maximum i 2 c speed (400 khz) is not achievable. in this case, maximum i 2 c speed will be approximately 260 khz. 2. data based on standard i 2 c protocol requirement, not tested in production. 3. the maximum hold time of the start condition has only to be met if the interface does not stretch the low period of scl signal. 4. the device must internally provide a hol d time of at least 300ns for the sda si gnal in order to bridge the undefined region of the falling edge of scl.
st72321xx-auto electrical characteristics doc id 13829 rev 1 215/243 figure 96. typical application with i 2 c bus and timing diagram (1) 1. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . the following table provides the values to be written in the i2cccr register to obtain the required i 2 c scl line frequency. legend: r p = external pull-up resistance f scl = i 2 c speed note: - for speeds around 200 khz, the achieved speed can have a 5% tolerance. - for other speed ranges, the achieved speed can have a 2% tolerance. the above variations depend on the accuracy of the external components used. repeated start start stop start t f(sda) t r(sda) t su(sda) t h(sda) t f(sck) t r(sck) t w(sckl) t w(sckh) t h(sta) t su(sto) t su(sta) t w(sto:sta) sda sck 4.7k ? sdai st72xxx scli v dd 100 ? 100 ? v dd 4.7k ? i 2 cbus table 134. scl frequency table f scl (khz) i2cccr value f cpu =4mhz f cpu =8mhz v dd = 4.1v v dd = 5v v dd = 4.1v v dd = 5v r p =3.3k ? r p =4.7k ? r p =3.3k ? r p =4.7k ? r p =3.3k ? r p =4.7k ? r p =3.3k ? r p =4.7k ? 400 not achievable 83h 300 not achievable 85h 200 83h 8ah 89h 8ah 100 10h 24h 23h 24h 23h 50 24h 4ch 20 5fh ffh
electrical characteristics st72321xx-auto 216/243 doc id 13829 rev 1 19.12 10-bit adc characteristics subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. table 135. 10-bit adc characteristics symbol parameter conditions min typ max unit f adc adc clock frequency 0.4 2 mhz v aref analog reference voltage 0.7*v dd < v aref < v dd 3.8 v dd v v ain conversion voltage range (1) v ssa v aref i lkg positive input leakage current for analog input -40c < t a < 85c range 250 na other t a ranges 1 a i lkg negative input leakage current on robust analog pins (2) v in st72321xx-auto electrical characteristics doc id 13829 rev 1 217/243 figure 99. typical a/d converter application 19.12.1 analog power supp ly and reference pins depending on the mcu pin count, the package may feature separate v aref and v ssa analog power supply pins. these pins supply power to the a/d converter cell and function as the high and low reference voltages for the conversion. separation of the digital and analog power pins allow board designers to improve a/d performance. conversion accuracy can be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines (see section 19.12.2: general pcb design guidelines ). figure 97. r ain maximum versus f adc with c ain =0pf (1) figure 98. recommended c ain and r ain values (1) 1. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (3pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. 1. this graph shows that, depending on the input signal variation (f ain ), c ain can be increased for stabilization time and decreased to allow the use of a larger serial resistor (r ain) . 0 5 10 15 20 25 30 35 40 45 0103070 c parasitic (pf) max. r ain (kohm) 2 mhz 1 mhz 0.1 1 10 100 1000 0.01 0.1 1 10 f ain (khz) max. r ain (kohm) cain 10 nf cain 22 nf cain 47 nf ainx st72xxx v dd i lkg v t 0.6v v t 0.6v c adc 12pf v ain r ain 10-bit a/d conversion 2k ?? max ? c ain
electrical characteristics st72321xx-auto 218/243 doc id 13829 rev 1 19.12.2 general pcb design guidelines to obtain best results, some general design and layout rules should be followed when designing the application pcb to shield the noise-sensitive, analog physical interface from noise-generating cmos logic signals. use separate digital and analog planes. the analog ground plane should be connected to the digital ground plane via a single point on the pcb. filter power to the analog power planes. it is recommended to connect capacitors, with good high frequency characteristics, between the power and ground lines, placing 0.1f and optionally, if needed 10pf capacitors as close as possible to the st7 power supply pins and a 1 to 10f capacitor close to the power source (see figure 100 ). the analog and digital power supplies should be connected in a star network. do not use a resistor, as v aref is used as a reference voltage by the a/d converter and any resistance would cause a voltage drop and a loss of accuracy. properly place components and route the signal traces on the pcb to shield the analog inputs. analog signals paths should run over the analog ground plane and be as short as possible. isolate analog signals from digital signals that may switch while the analog inputs are being sampled by the a/d converter. do not toggle digital outputs on the same i/o port as the a/d input being converted. figure 100. power supply filtering v ss v dd v dd st72xxx v aref v ssa power supply source st7 digital noise filtering external noise filtering 1 to 10f 0.1f 0.1f +
st72321xx-auto electrical characteristics doc id 13829 rev 1 219/243 19.12.3 adc accuracy conditions: v dd =5v (1) figure 101. adc error classification table 136. adc accuracy symbol parameter (1) 1. adc accuracy versus negative injection current: in jecting negative current may reduce the accuracy of the conversion being performed on another analog input. any positive injection current with in the limits specified for i inj(pin) and ? i inj(pin) in section 19.8 does not affect the adc accuracy. conditions typ max (2) 2. data based on characterization results, monitored in production to guarantee 99.73% within max value from -40c to 125c ( 3 ?? distribution limits). unit |e t | total unadjusted error cpu in run mode @ f adc 2 mhz 34 lsb |e o | offset error 2 3 |e g | gain error 0.5 3 |e d | differential linearity error 12 |e l | integral linearity error e o e g 1lsb ideal 1lsb ideal v aref v ssa ? 1024 -------------------------------------------- = v in (lsb ideal ) digital result adcdr 1023 1022 1021 5 4 3 2 1 0 7 6 1234567 1021 1022 1023 1024 (1) (2) e t e d e l (3) v aref v ssa legend: (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t = total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o = offset error: deviation between the first actual transition and the first ideal one. e g = gain error: deviation between the last ideal transition and the last actual one. e d = differential linearity error: maximum deviation between actual steps and the ideal one. e l = integral linearity error: maximum deviation between any actual transition and the end point correlation line.
package characteristics st72321xx-auto 220/243 doc id 13829 rev 1 20 package characteristics figure 102. 64-pin (14x14) low profile quad flat package outline table 137. 64-pin (14x14) low profile quad flat package mechanical data dimension mm inches min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 0.200 0.0035 0.0079 d 16.000 0.6299 d1 14.000 0.5512 e 16.000 0.6299 e1 14.000 0.5512 e 0.800 0.0315 ? 0 3.5 7 0 3.5 7 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394 c ? l l1 e b a a1 a2 e e1 d d1
st72321xx-auto package characteristics doc id 13829 rev 1 221/243 figure 103. 64-pin (10x10) low profile quad flat package outline table 138. 64-pin (10x10) low profile quad flat package mechanical data dimension mm inches min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 d 12.000 0.4724 d1 10.000 0.3937 e 12.000 0.4724 e1 10.000 0.3937 e 0.500 0.0197 ? 0 3.5 7 0 3.5 7 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394 a a2 a1 c ? l1 l e e1 d d1 e b
package characteristics st72321xx-auto 222/243 doc id 13829 rev 1 20.1 thermal characteristics 20.2 ecopack information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 20.3 packaging for automatic handling the devices can be supplied in trays or with tape and reel conditioning. tape and reel conditioning can be ordered with pin 1 left-oriented or right-oriented when facing the tape sprocket holes as shown in figure 104 . figure 104. pin 1 orientation in tape and reel conditioning see also section figure 105.: st72f321xxx-auto flash commercial product structure on page 226 and figure 106: st72p321xxx-auto fastrom commercial product structure on page 228 . table 139. thermal characteristics symbol ratings value unit r thja package thermal resistance (junction to ambient) lqfp64 14x14 lqfp64 10x10 lqfp44 10x10 47 50 52 c/w p d power dissipation (1) 1. the maximum power dissipation is obtained from the formula p d = (t j -t a ) / r thja . the power dissipation of an application can be defined by the user with the formula: p d =p int +p port where p int is the chip internal power (i dd xv dd ) and p port is the port power dissipation depe nding on the ports used in the application. 500 mw t jmax maximum junction temperature (2) 2. the maximum chip-junction temperature is based on technology characteristics. 150 c right orientation (eia 481-c compliant) left orientation pin 1 pin 1
st72321xx-auto device configuration and ordering information doc id 13829 rev 1 223/243 21 device configuration and ordering information each device is available for production in user programmable versions (flash) as well as in factory coded versions (rom/fastrom). st72321-auto devices are rom versions, st72p321-auto devices are factory advanced service technique rom (fastrom) versions: they are factory-programmed hdflash devices. flash devices are shipped to customers with a default content, whereas rom/fastrom factory coded parts contain the code supplied by the customer. this implies that flash devices have to be configured by the customer using the option bytes while the rom/fastrom devices are factory-configured. detailed device configuration and ordering information is presented in the following section 21.1: flash devices and section 21.2: rom device ordering information and transfer of customer code . 21.1 flash devices 21.1.1 flash configuration the option bytes allow the hardware configuration of the microcontroller to be selected. they have no address in the memory map and can be accessed only in programming mode (for example, using a standard st7 programming tool). the default content of the flash is fixed to ffh. to program the flash devices directly using icp, flash devices are shipped to customers with the internal rc clock source enabled. in masked rom devices, the option bytes are fixed in hardware by the rom code (see option list). table 140. flash option bytes static option byte 0 s tatic option byte 1 7654321076543210 wdg res vd res pkg0 fmp_r pkg1 rstc osctype oscrange plloff haltsw 10 10210 default value: 1110011111101111
device configuration and ordering information st72321xx-auto 224/243 doc id 13829 rev 1 table 141. option byte 0 bit description bit name function opt7 wdg halt watchdog and halt mode this option bit determines if a reset is generated when entering halt mode while the watchdog is active. 0: no reset generation when entering halt mode 1: reset generation when entering halt mode opt6 wdg sw hardware or software watchdog this option bit selects the watchdog type. 0: hardware (watchdog always enabled) 1: software (watchdog to be enabled by software) opt5 - reserved, must be kept at default value. opt4:3 vd[1:0] voltage detection these option bits enable the voltage detection block (lvd and avd) with a selected threshold for the lvd and avd (evd + avd). 00: selected lvd = highest threshold (v dd ~4v) 01: selected lvd = medium threshold (v dd ~3.5v) 10: selected lvd = lowest threshold (v dd ~3v) 11: lvd and avd off caution : if the medium or low threshol ds are selected, the detection may occur outside the specified operating voltage range. below 3.8v, device operation is not guaranteed. for details on the avd and lvd threshold levels refer to table 19.3.2: operating conditions with low voltage detector (lvd) . opt2 - reserved, must be kept at default value. opt1 pkg0 package selection bit 0 this option bit is used with the pkg1 bit to select the package (see table 143: package selection (opt7) ). opt0 fmp_r flash memory readout protection readout protection, when selected , provides a protection against program memory content extraction and against write access to flash memory. erasing the option bytes when the fmp_r option is selected causes the whole user memory to be erased first, after which the device can be reprogrammed. refer to section 4.3.1: readout protection on page 30 and the st7 flash programming reference manual for more details. note: readout protection is not supported if lvd is enabled. 0: readout protection enabled 1: readout protection disabled
st72321xx-auto device configuration and ordering information doc id 13829 rev 1 225/243 note: on the chip, each i/o port has up to eight pads. pads that are not bonded to external pins are in input pull-up configuration after reset. the configuration of these pads must be kept at reset state to avoid added current consumption. table 142. option byte 1 bit description bit name function opt7 pkg1 package selection bit 1 this option bit, with the pkg0 bit, selects the package (see table 143: package selection (opt7) ). opt6 rstc reset clock cycle selection this option bit selects the number of cpu cycles applied during the reset phase and w hen exiting halt mode. fo r resonator oscillators, it is advised to select 4096 due to the long crystal stabilization time. 0: reset phase with 4096 cpu cycles 1: reset phase with 256 cpu cycles opt5:4 osctype[1:0] oscillator type these option bits select the st7 main clock source type. 00: clock source = resonator oscillator 01: reserved 10: clock source = internal rc oscillator 11: clock source = external source opt3:1 oscrange[2:0] oscillator range when the resonator oscillator type is selected, these option bits select the resonator oscillator current source corresponding to the frequency range of the resonator used. otherwise, these bits are used to select the normal operating frequency range. 000: typ. frequency range = lp (1 ~ 2 mhz) 001: typ. frequency range = mp (2 ~ 4 mhz) 010: typ. frequency range = ms (4 ~ 8 mhz) 011: typ. frequency range = hs (8 ~ 16 mhz) opt0 plloff pll activation this option bit activates the pll which allows multiplication by two of the main input clock frequency. the pll must not be used with the internal rc oscillator or with external clock source. the pll is guaranteed only with an input frequency between 2 and 4 mhz. 0: pll x2 enabled 1: pll x2 disabled caution : the pll can be enabled only if the oscrange (opt3:1) bits are configured to ?mp 2 ~ 4 mhz?. ot herwise, the device functionality is not guaranteed. table 143. package selection (opt7) version selected package pkg1 pkg0 (a)r lqfp64 1 0 jlqfp44 00
device configuration and ordering information st72321xx-auto 226/243 doc id 13829 rev 1 21.1.2 flash ordering information the following figure 105 serves as a guide for ordering. figure 105. st72f321xxx-auto flash commercial product structure 1. for a list of available options (e.g. memory size, package) and or derable part numbers or for further information on any aspect of this device, please go to www.st.com or contact the st sales office nearest to you. st72 f 321 r 9 t a x s product class st72 microcontroller pin count ar = 64 pins 10 x 10 mm r = 64 pins 14 x 14 mm j = 44 pins 10 x 10 mm package type t = lqfp example: sub-family type 321 = 321 sub-family family type f = flash temperature range a = -40 c to 85 c c = -40 c to 125 c program memory size 6 = 32 kbytes 7 = 48 kbytes 9 = 60 kbytes tape and reel conditioning options (left blank if tray) tr or r = pin 1 left-oriented tx or x = pin 1 right-oriented (eia 481-c compliant) ecopack/fab code blank or e = lead-free ecopack ? phoenix fab s = lead-free ecopack ? catania fab
st72321xx-auto device configuration and ordering information doc id 13829 rev 1 227/243 21.2 rom device ordering informat ion and transfer of customer code customer code is made up of the rom/fastrom contents and the list of the selected options (if any). the rom/fastrom contents are to be sent on diskette, or by electronic means, with the s19 hexadecimal file generated by the development tool. all unused bytes must be set to ffh. complete the appended option list on page 230 to communicate the selected options to stmicroelectronics and check for regular updates of the option list on the st website or ask your st representative. refer to application note an1635 for information on the counter listing returned by st after code has been transferred. the following figure 106 and figure 107 serve as guides for ordering. the stmicroelectronics sales organization will be pleased to provide detailed information on contractual points. caution: the readout protection binary value is inverted between rom and flash products. the option byte checksum will differ between rom and flash.
device configuration and ordering information st72321xx-auto 228/243 doc id 13829 rev 1 figure 106. st72p321xxx-auto fastrom commercial product structure st72 p 321 t a /xxx x s product class st72 microcontroller package type t = lqfp example: sub-family type 321= 321 sub-family family type p = fastrom temperature range a = -40 c to 85 c c = -40 c to 125 c tape and reel conditioning options (left blank if tray) tr or r = pin 1 left-oriented tx or x = pin 1 right-oriented (eia 481-c compliant) ecopack/fab code blank or e = lead-free ecopack ? phoenix fab s = lead-free ecopack ? catania fab code name defined by stmicroelectronics. denotes rom code, pinout and program memory size.
st72321xx-auto device configuration and ordering information doc id 13829 rev 1 229/243 figure 107. st72321xxx-auto rom commercial product structure st72 321 t a /xxx x s product class st72 microcontroller package type t = lqfp example: 321 = 321sub-family temperature range a = -40 c to 85 c c = -40 c to 125 c tape and reel conditioning options (left blank if tray) tr or r = pin 1 left-oriented tx or x = pin 1 right-oriented (eia 481-c compliant) ecopack/fab code blank or e = lead-free ecopack ? phoenix fab s = lead-free ecopack ? catania fab code name defined by stmicroelectronics. denotes rom code, pinout and program memory size.
device configuration and ordering information st72321xx-auto 230/243 doc id 13829 rev 1 st72321-auto microcontroller fastrom/rom option list (last update august 2007) customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . address: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contact: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . phone no: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reference/rom code* : . . . . . . . . . . . . . . . . . . . . . . . . *the rom code name is assig ned by stmicroelectronics. rom code must be sent in .s19 format. .hex extension cannot be processed. device type/memory size/package (check only one option): ------------------------------------------------------------------------------------------------------------------------------- ----------------------- fastrom device: 60k 48k 32k ------------------------------------------------------------------------------------------------------------------------------- ----------------------- lqfp44 10x10: [ ] st72p321(j9)t [ ] st72p321(j7)t lqfp64 10x10: [ ] st72p321(ar9)t [ ] st72p321(ar7)t [ ] st72p321(ar6)t lqfp64 14x14: [ ] st72p321(r9)t [ ] st72p321(r7)t [ ] st72p321(r6)t ------------------------------------------------------------------------------------------------------------------------------- ------------------------ ------------------------------------------------------------------------------------------------------------------------------- ------------------------ rom device: 60k 48k 32k ------------------------------------------------------------------------------------------------------------------------------- ------------------------ lqfp44 10x10: [ ] st72321(j9)t [ ] st72321(j7)t lqfp64 10x10: [ ] st72321(ar9)t [ ] st72321(ar7)t [ ] st72321(ar6)t lqfp64 14x14: [ ] st72321(r9)t [ ] st72321(r7)t [ ] st72321(r6)t ------------------------------------------------------------------------------------------------------------------------------- ------------------------ conditioning for lqfp package (check only one option): [ ] tape & reel [ ] tray temperature range : [ ] a (-40c to +85c) [ ] b (-40c to +105c) [ ] c (-40c to +125c) special marking: [ ] no [ ] yes "_ _ _ _ _ _ _ _ _ _ " (10 characters max) authorized characters are letters, di gits, '.', '-', '/' and spaces only. clock source selection: [ ] resonator: [ ] lp: low power resonator (1 to 2 mhz) [ ] mp: medium power resonator (2 to 4 mhz) [ ] ms: medium speed resonator (4 to 8 mhz) [ ] hs: high speed resonator (8 to 16 mhz) [ ] internal rc (1) [ ] external clock (sets mp medium power resonator in option byte) pll (2) [ ] disabled [ ] enabled lvd reset [ ] disabled [ ] high threshold [ ] med.threshold [ ] low threshold reset delay [ ] 256 cycles [ ] 4096 cycles watchdog selection [ ] software activation [ ] hardware activation watchdog reset on halt: [ ] reset [ ] no reset readout protection (3) : [ ] disabled [ ] enabled date. . . . . . . . . . . . . . signature . . . . . . . . . . . . . . . . . . . . . . . . . . note 1: internal rc can only be used if lvd is enabled note 2: pll must not be enabled if internal rc or external clock is selected. note 3: readout protection not supported if lvd is enabled. caution: the readout protection binary value is inverted betw een rom and flash products. the option byte checksum will differ between rom and flash. please download the latest version of this option list from www.st.com.
st72321xx-auto device configuration and ordering information doc id 13829 rev 1 231/243 21.3 development tools 21.3.1 introduction development tools for the st7 microcontrollers include a complete range of hardware systems and software tools from stmicroelectronics and third-party tool suppliers. the range of tools includes solutions to help you evaluate microcontroller peripherals, develop and debug your application, and program your microcontrollers. 21.3.2 evaluation tool s and starter kits st offers complete, affordable starter kits and full-featured evaluation boards that allow you to evaluate microcontroller features and quickly start developing st7 applications. starter kits are complete, affordable hardware/software tool packages that include features and samples to help you quickly start developing your application. st evaluation boards are open-design, embedded systems, which are developed and documented to serve as references for your application design. they include sample application software to help you demonstrate, learn about and implement your st7?s features. 21.3.3 development and debugging tools application development for st7 is supported by fully optimizing c compilers and the st7 assembler-linker toolchain, which are all se amlessly integrated in the st7 integrated development environments in order to facilit ate the debugging and fine-tuning of your application. the cosmic c comp iler is available in a free version that outputs up to 16 kbytes of code. the range of hardware tools includes cost effective st7-dvp3 series emulators. these tools are supported by the st7 toolset from stmicroelectronics, which includes the stvd7 integrated development environment (ide) with high-level language debugger, editor, project manager and integrated programming interface. 21.3.4 programming tools during the development cycle, the st7-dvp3 and st7-emu3 series emulators and the rlink provide in-circuit prog ramming capability for programmi ng the flash microcontroller on your application board. st also provides a low-cost dedicated in-circuit programmer, the st7-stick, as well as st7 socket boards which provide all the sockets required for programming any of the devices in a specific st7 subfamily on a platform that can be used with any tool with in- circuit programming capability for st7. for production programming of st7 devices, st?s third-party tool partners also provide a complete range of gang and automated programming solutions, which are ready to integrate into your production environment. for additional ordering codes for spare parts, accessories and tools available for the st7 (including from third party manufacturers), refer to the online product selector at www.st.com/mcu.
device configuration and ordering information st72321xx-auto 232/243 doc id 13829 rev 1 21.3.5 socket and emulator adapter information for information on the type of socket that is supplied with the emulator, refer to the suggested list of sockets in ta b l e 1 4 5 . note: before designing the board layout, it is recommended to check the overall dimensions of the socket as they may be greater than the dimensions of the device. for footprint and other mechanical information about these sockets and adapters, refer to the manufacturer?s datasheet. related documentation st7 visual develop software key debugging features (an 978) st7 visual develop for st7 cosmic c toolset users (an 1938) st7 visual develop for st7 assembler linker toolset users (an 1940) table 144. stmicroelectronics development tools supported products emulation programming st7 dvp3 series st7 emu3 series icc socket board emulator connection kit emulator active probe and t.e.b. st72521m, st72f521m st7mdt20- dvp3 st7mdt20- t80/dvp st7mdt20m- emu3 st7mdt20m- teb st7sb20m/xx (1) st72521r, st72f521r st7mdt20- t64/dvp st72521ar, st72f521ar st7mdt20- t6a/dvp st72321ar, st72f321ar st7mdt20- dvp3 st7mdt20- t6a/dvp st7mdt20m- emu3 st7mdt20m- teb st7sb20m/xx (2) st72321r, st72f321r st7mdt20- t64/dvp st72321j, st72f321j st7mdt20- t44/dvp st7mdt20j- emu3 st7mdt20j- teb st7sb20j/xx (2) 1. add suffix /eu, /uk, /us for the power supply of your region. 2. add suffix /eu, /uk, /us for the power supply of your region. table 145. suggested list of socket types device socket (supplied with st7mdt20m-emu3) emulator adapter (supplied with st7mdt20m-emu3) lqfp80 14 x 14 yamaichi ic1 49-080-*51-*5 yamaichi icp-080-7 lqfp64 14 x14 cab 3303262 cab 3303351 lqfp64 10 x10 yamaichi ic149- 064-*75-*5 yamaichi icp-064-6 lqfp44 10 x10 yamaichi ic149- 044-*52-*5 yamaichi icp-044-5
st72321xx-auto device configuration and ordering information doc id 13829 rev 1 233/243 21.4 st7 application notes all relevant st7 application notes can be found on www.st.com.
known limitations st72321xx-auto 234/243 doc id 13829 rev 1 22 known limitations 22.1 all flash and rom devices 22.1.1 external rc option the external rc clock source option described in previous datasheet revisions is no longer supported and has been removed from this specification. 22.1.2 safe connection of osc1/osc2 pins the osc1 and/or osc2 pins must not be left unconnected, otherwise the st7 main oscillator may start and, in this configuration, co uld generate an f osc clock frequency in excess of the allowed maximum (> 16 mhz), putting the st7 in an unsafe/undefined state. refer to section 6.4: multi-osc illator (mo) on page 38 . 22.1.3 reset pin protection with lvd enabled as mentioned in note 2 below figure 90: reset pin protecti on when lvd is enabled on page 208 , when the lvd is enabled, it is recommended not to connect a pull-up resistor or capacitor. a 10nf pull-down capacitor is re quired to filter nois e on the reset line. 22.1.4 unexpected reset fetch if an interrupt request occurs while a ?pop cc? instruction is ex ecuted, the interrupt controller does not reco gnize the source of th e interrupt and, by def ault, passes the reset vector address to the cpu. workaround to solve this issue, a ?pop cc? instruction must always be preceded by a ?sim? instruction. 22.1.5 external interrupt missed to avoid any risk of generating a parasitic interrupt, the edge detector is automatically disabled for one clock cycle during an access to either ddr and or. any input signal edge during this period will not be detect ed and will not generate an interrupt. this case can typically occur if the application refreshes the port configuration registers at intervals during runtime. workaround the workaround is based on software checking the level on the interrupt pin before and after writing to the pxor or pxddr registers. if there is a level change (depending on the sensitivity programmed for this pin) the interr upt routine is invoked us ing the call instruction with three extra push instructions before executing the interrupt routine (this is to make the call compatible with the iret instruction at the end of the interrupt service routine). but detection of the level change does not make sure that edge occurs during the critical 1 cycle duration and the interrupt has been missed. this may lead to occurrence of same interrupt twice (one hardware and another with software call).
st72321xx-auto known limitations doc id 13829 rev 1 235/243 to avoid this, a semaphore is set to ?1? before checking the level change. the semaphore is changed to level '0' inside the interrupt routine. when a level change is detected, the semaphore status is checked. if it is ?1?, it means that the last interrupt has been missed. in this case, the interrupt routine is invoked with the call instruction. there is another possible case, that is, if pxor or pxddr are written to with global interrupts disabled (interrupt mask bit set). in this case, the semaphore is changed to ?1? when the level change is detected. detecting a missed interrupt is done after the global interrupts are enabled (interrupt mask bit reset) and by checking the status of the semaphore. if it is ?1?, it means that the last interrupt was missed and the interrupt routine is invoked with the call instruction. to implement the workaround, the following software sequence is to be followed for writing into the pxor/pxddr registers. the example is for port pf1 with falling edge interrupt sensitivity. the software sequen ce is given for both cases (glo bal interrupts disabled / global interrupts enabled): case 1: writing to pxor or pxddr wi th global interrupts enabled: ld a,#01 ld sema,a ; set the semaphore to '1' ld a,pfdr and a,#02 ld x,a ; store the level before writing to pxor/pxddr ld a,#$90 ld pfddr,a ; write to pfddr ld a,#$ff ld pfor,a ; write to pfor ld a,pfdr and a,#02 ld y,a ; store the level after writing to pxor/pxddr ld a,x ; check for falling edge cp a,#02 jrne out tnz y jrne out ld a,sema
known limitations st72321xx-auto 236/243 doc id 13829 rev 1 ; check the semaphore status if edge is detected cp a,#01 jrne out call call_routine ; call the interrupt routine out:ld a,#00 ld sema,a .call_routine ; entry to call_routine push a push x push cc .ext1_rt ; entry to interrupt routine ld a,#00 ld sema,a iret case 2: writing to pxor or pxddr with global interrupts disabled: sim ; set the interrupt mask ld a,pfdr and a,#$02 ld x,a ; store the level before writing to pxor/pxddr ld a,#$90 ld pfddr,a ; write into pfddr ld a,#$ff ld pfor,a ; write to pfor ld a,pfdr and a,#$02 ld y,a ; store the level after writing to pxor/pxddr ld a,x
st72321xx-auto known limitations doc id 13829 rev 1 237/243 ; check for falling edge cp a,#$02 jrne out tnz y jrne out ld a,#$01 ld sema,a ; set the semaphore to '1' if edge is detected rim ; reset the interrupt mask ld a,sema ; check the semaphore status cp a,#$01 jrne out call call_routine ; call the interrupt routine rim out: rim jp while_loop .call_routine ; entry to call_routine push a push x push cc .ext1_rt ; entry to interrupt routine ld a,#$00 ld sema,a iret
known limitations st72321xx-auto 238/243 doc id 13829 rev 1 22.1.6 clearing active interrupts outside interrupt routine when an active interrupt request occurs at the same time as the related flag is being cleared, an unwanted reset may occur. note: clearing the related interrupt mask will not generate an unwanted reset. concurrent interrupt context the symptom does not occur when the interrupts are handled normally, that is, when: the interrupt flag is cleared within its own interrupt routine the interrupt flag is cleared within any interrupt routine the interrupt flag is cleared in any part of the code while this interrupt is disabled if these conditions are not met, the symptom can be avoided by implementing the following sequence: perform sim and rim operation before and after resetting an active interrupt request. example: sim reset interrupt flag rim nested interrupt context the symptom does not occur when the interrupts are handled normally, that is, when: the interrupt flag is cleared within its own interrupt routine the interrupt flag is cleared within any interrupt routine with higher or identical priority level the interrupt flag is cleared in any part of the code while this interrupt is disabled if these conditions are not met, the symptom can be avoided by implementing the following sequence: push cc sim reset interrupt flag pop cc
st72321xx-auto known limitations doc id 13829 rev 1 239/243 22.1.7 sci wrong break duration description a single break characte r is sent by setting and resetting the sbk bit in the scicr2 register. in some cases, the break character may have a longer duration than expected: 20 bits instead of 10 bits if m = 0 22 bits instead of 11 bits if m = 1 in the same way, as long as the sbk bit is se t, break characters are sent to the tdo pin. this may lead to generating one break more than expected. occurrence the occurrence of the problem is random and proportional to the baud rate. with a transmit frequency of 19200 baud (f cpu = 8 mhz and scibrr = 0xc9), the wrong break duration occurrence is around 1%. workaround if this wrong duration is not compliant with th e communication protocol in the application, software can request that an idle line be generated before the break character. in this case, the break duration is always correct assuming the application is not doing anything between the idle and the break. this can be ensured by temporarily disabling interrupts. the exact sequence is: disable interrupts reset and set te (idle request) set and reset sbk (break request) re-enable interrupts 22.1.8 16-bit timer pwm mode in pwm mode, the first pwm pulse is missed after writing the value fffch in the oc1r register (oc1hr, oc1lr). it leads to either full or no pwm during a period, depending on the olvl1 and olvl2 settings.
known limitations st72321xx-auto 240/243 doc id 13829 rev 1 22.1.9 timd set simultaneo usly with oc interrupt if the 16-bit timer is disabled at the same time the output compare event occurs, the output compare flag then gets locked and cannot be cleared before the timer is enabled again. impact on the application if the output compare interrupt is enabled, then the output compare flag cannot be cleared in the timer interrupt routine. consequently, the interrupt service routine is called repeatedly. workaround disable the timer interrupt before disabling the timer. again while enabling, first enable the timer, then the timer interrupts. perform the following to disable the timer: ? tacr1 or tbcr1 = 0x00h; // disable the compare interrupt ? tacsr | or tbcsr | = 0x40; // disable the timer perform the following to enable the timer again: ? tacsr & or tbcsr & = ~0x40; // enable the timer ? tacr1 or tbcr1 = 0x40; // enable the compare interrupt 22.1.10 i 2 c multimaster in multimaster configurations, if the st7 i2c receives a start condition from another i2c master after the start bit is set in the i2ccr register and before the start condition is generated by the st7 i2c, it may ignore the start condition from the other i2c master. in this case, the st7 master will receive a nack from the other device. on reception of the nack, st7 can send a restart and slave address to re-initiate communication. 22.1.11 readout pr otection with lvd the lvd is not supported if readout protection is enabled 22.2 all flash devices 22.2.1 internal rc oscillator with lvd the internal rc can only be used if lvd is enabled. 22.3 limitations specific to rom devices 22.3.1 lvd operation depending on the operating conditions, especially the v dd ramp up speed and ambient temperature, in some cases the lvd may not start. when this occurs, the mcu may operate outside the guaranteed functional area (see figure 73 ) without being forced into reset state. in this case, proper use of the watchdog may make it possible to recover through a watchdog reset and allow normal operations to resume.
st72321xx-auto known limitations doc id 13829 rev 1 241/243 consequently, the lvd function is not guaranteed in the current silicon revision. for complete security, an external reset circuit must be added. 22.3.2 lvd startup behavior when the lvd is enabled, the mcu reaches its authorized operating voltage from a reset state. however, in some devices, the reset state is released when v dd is approximately between 0.8v and 1.5v. as a consequence, the i/os may toggle when v dd is within this window. this may be an issue especially for applicat ions where the mcu drives power components. figure 108. lvd startup behavior 22.3.3 avd not supported on some devices with a specific v dd ramp up speed the avd may not start. as a result it cannot generate interrupts when v dd rises and falls. 22.3.4 internal rc oscillator operation internal rc oscillator operation is not supported in rom devices. 22.3.5 external clock source with pll external clock source is not supported with the pll enabled. 22.3.6 pull-up not present on pe2 unlike st72f321 flash devices, st72321 rom devices have no weak pull-up on port pe2. in lqfp44 rom devices, the pe2 pad is not connected to an internal pull-up like other unbonded pads. it is recommended to configure it as output push-pull to avoid added current consumption. 22.3.7 readout prot ection with lvd the lvd is not supported if readout protection is enabled. 5v 1.5v v it+ 0.8v lvd reset v d d window t
revision history st72321xx-auto 242/243 doc id 13829 rev 1 23 revision history table 146. document revision history date revision changes 05-aug-2010 1 initial release
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